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11. 发明授权

US06541327B1 Method to form self-aligned source/drain CMOS device on insulated staircase oxide 失效
标题翻译：在绝缘阶梯氧化物上形成自对准源极/漏极CMOS器件的方法
公开(公告)号：US06541327B1
公开(公告)日：2003-04-01
申请号：US09760123
申请日：2001-01-16
申请人： Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
发明人： Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
IPC分类号： H01L218238
CPC分类号： H01L29/66492 , H01L21/823814 , H01L29/41783 , H01L29/665 , H01L29/66575
摘要： A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.
摘要翻译：一种在绝缘层中的阶梯形开口形成升高的源极/漏极（S / D）的方法。栅极结构形成在衬底上。栅极结构优选由栅极电介质层，栅电极，第一间隔物和硬掩模组成。在衬底和栅极结构之上形成第一绝缘层。形成抗蚀剂层，其具有在栅极结构上方的开口以及与栅极结构相邻的横向区域。我们通过抗蚀剂层中的开口蚀刻绝缘层。蚀刻去除绝缘层的第一厚度以形成源极/漏极（S / D）开口。我们移除第一个垫片和硬掩模以形成一个源极/漏极（S / D）接触开口。我们通过源极/漏极（S / D）接触开口将离子注入到衬底中，以形成轻掺杂的漏极区。我们在源极/漏极（S / D）接触开口和源极/漏极（S / D）开口中的栅电极和栅极电介质的侧壁和绝缘层的侧壁上形成第二间隔物。在栅电极，绝缘层上沉积导电层。导电层被平坦化以暴露绝缘层，以在阶梯形绝缘层上形成升高的源极/漏极（S / D）块。

12. 发明授权

US06531750B2 Shallow junction transistors which eliminating shorts due to junction spiking 失效
标题翻译：浅结结晶体管，消除由于接头尖峰引起的短路
公开(公告)号：US06531750B2
公开(公告)日：2003-03-11
申请号：US09943306
申请日：2001-08-31
申请人： Lap Chan , Cher Liang Cha , Ravishankar Sundaresan
发明人： Lap Chan , Cher Liang Cha , Ravishankar Sundaresan
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L21/28044 , H01L29/41775 , H01L29/41783 , H01L29/456 , H01L29/4916 , H01L29/4941 , H01L29/665 , H01L29/66545
摘要： A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions. The second electrode layer is etched through to form separate conductive connections. An intermetal dielectric layer is deposited. The intermetal dielectric layer is etched through to form contact openings. A metal layer is deposited and etched through to form separate metal interconnects. A passivation layer is deposited, and the integrated circuit is completed.
摘要翻译：实现了形成浅结MOSFET的方法。栅极氧化层形成在衬底上。沉积多晶硅或金属的第一电极层。沉积氮化硅层。氮化硅层和第一电极层被蚀刻通过以形成临时MOSFET栅极。将离子注入到衬底中以形成轻掺杂的结。沉积间隔层。间隔层和栅极氧化物层被各向异性地蚀刻以形成侧壁间隔物。将离子注入到衬底中以形成重掺杂的结。蚀刻掉氮化硅层。多晶硅或金属的第二电极层沉积在衬底，侧壁间隔物和第一多晶硅层上。将第二电极层抛光到侧壁间隔物的顶表面以完成MOSFET并形成永久栅极和与源极和漏极结的导电连接。蚀刻第二电极层以形成分开的导电连接。沉积金属间电介质层。金属间电介质层被蚀刻穿过以形成接触开口。金属层被沉积并蚀刻通过以形成单独的金属互连。沉积钝化层，并且集成电路完成。

13. 发明授权

US06436770B1 Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation 失效
标题翻译：通过使用选择性外延和使用注入的源极/漏极首先形成沟道来控制垂直晶体管的沟道长度的方法
公开(公告)号：US06436770B1
公开(公告)日：2002-08-20
申请号：US09721720
申请日：2000-11-27
申请人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
发明人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
IPC分类号： H01L21332
CPC分类号： H01L29/7827 , H01L29/42356 , H01L29/66666
摘要： A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region. A channel length is between the top of the source region and the drain region. We form an interlevel dielectric layer over the barrier layer, the gate layer, and the conductive plug. Contacts are formed through the interlevel dielectric layer to the doped gate regions, the drain region and the source region.
摘要翻译：一种垂直MOS晶体管的方法，其垂直沟道宽度可以被精确地限定和控制。在衬底中形成隔离区。隔离区限定有效区域。然后，我们在活动区域中形成一个源区域。在有源区域和隔离区域上形成介电层。我们在电介质层上形成阻挡层。我们在屏障层形成一个开口。在开口中形成栅极层。我们在导电层和阻挡层上形成绝缘层。我们通过绝缘层，栅极层和电介质层形成栅极开口以暴露源极区域。栅极电介质隔离物形成在栅极层的侧壁上。然后，我们形成一个填充门开口的导电塞。绝缘层被去除。我们在导电插塞的顶部和侧部形成漏极区，并在栅极层中形成掺杂的栅极区。导电插塞的其余部分包括沟道区域。沟道长度在源极区域的顶部和漏极区域之间。我们在阻挡层，栅极层和导电插塞上形成层间电介质层。通过层间介质层与掺杂栅极区，漏极区和源极区形成触点。

14. 发明授权

US06323125B1 Simplified dual damascene process utilizing PPMSO as an insulator layer 失效
标题翻译：使用PPMSO作为绝缘体层的简化双镶嵌工艺
公开(公告)号：US06323125B1
公开(公告)日：2001-11-27
申请号：US09282065
申请日：1999-03-29
申请人： Choi Pheng Soo , Wye Boon Loh , Lap Chan
发明人： Choi Pheng Soo , Wye Boon Loh , Lap Chan
IPC分类号： H01L214763
CPC分类号： H01L21/76825 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/3121 , H01L21/76808 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： Only one photo mask defines the metal trench and via region. The mask blocks the UV light in the trench and via area forming Plasma Polymerized Methylsilane Oxide (PPMSO) in the exposed areas. Two step RIE plasma treatment using chlorine gas and oxygen gas removes the Plasma Polymerized Methylsilane (PPMS) in the trench and via regions. Conductive metal is deposited. A CMP process polishes back both excess metal along with the PPMSO, at a similar rate, to form: conducting metal lines, interconnects, and via contacts without metal dishing.
摘要翻译：只有一个光罩定义了金属沟槽和通孔区域。掩模在暴露的区域中阻挡沟槽中的UV光和形成等离子聚合甲基硅烷氧化物（PPMSO）的通孔区域。使用氯气和氧气的两步RIE等离子体处理在沟槽和通孔区域中除去等离子体聚合甲基硅烷（PPMS）。导电金属被沉积。 CMP工艺以类似的速率抛光多余金属与PPMSO，以形成：导电金属线，互连和通孔触点，而不会金属凹陷。

15. 发明授权

US06319767B1 Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique 有权
标题翻译：用于通过等离子体灰化和硬掩蔽技术消除MIM电容器底金属图案化期间的顶部金属角成形的方法
公开(公告)号：US06319767B1
公开(公告)日：2001-11-20
申请号：US09798639
申请日：2001-03-05
申请人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
发明人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/31122 , H01L21/31144 , H01L21/32136 , H01L21/32139
摘要： A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A composite metal stack is formed comprising a first metal layer overlying the insulating layer, a capacitor dielectric layer overlying the first metal layer, a second metal layer overlying the capacitor dielectric layer, and a hard mask layer overlying the second metal layer. A first photoresist mask is formed overlying the hard mask layer. The composite metal stack is patterned using the first photoresist mask as an etching mask whereby the patterned first metal layer forms a bottom electrode of the capacitor. A portion of the first photoresist mask is removed by plasma ashing to form a second photoresist mask narrower than the first photoresist mask. The hard mask layer is patterned using the second photoresist mask as an etching mask. The second metal layer is patterned using the hard mask layer as an etching mask whereby the second metal layer forms a top electrode of the capacitor to complete fabrication of a metal-insulator-metal capacitor.
摘要翻译：描述了一种用于制造金属 - 绝缘体 - 金属电容器的方法，其中消除了图案化期间的顶部金属角成形。绝缘层设置在半导体衬底上。形成复合金属堆叠，其包括覆盖绝缘层的第一金属层，覆盖第一金属层的电容器电介质层，覆盖电容器电介质层的第二金属层和覆盖第二金属层的硬掩模层。第一光致抗蚀剂掩模形成在硬掩模层上。使用第一光致抗蚀剂掩模将复合金属堆叠图案化为蚀刻掩模，由此图案化的第一金属层形成电容器的底部电极。通过等离子体灰化除去第一光致抗蚀剂掩模的一部分，以形成比第一光致抗蚀剂掩模窄的第二光刻胶掩模。使用第二光致抗蚀剂掩模将硬掩模层图案化为蚀刻掩模。使用硬掩模层作为蚀刻掩模对第二金属层进行构图，由此第二金属层形成电容器的顶部电极，以完成金属 - 绝缘体 - 金属电容器的制造。

16. 发明授权

US06313008B1 Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon 失效
标题翻译：使用微加工技术形成气球形STI以去除重掺杂硅的方法
公开(公告)号：US06313008B1
公开(公告)日：2001-11-06
申请号：US09768486
申请日：2001-01-25
申请人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
发明人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said substrate through said isolation opening to form a Si damaged or doped first region. The first region is selectively etching to form a hole. The hole is filled with an insulating material to form a balloon shaped shallow trench isolation (STI) region. The substrate has active areas between said balloon shaped shallow trench isolation (STI) regions. The second embodiment differs from the first embodiment by forming a trench in the substrate before the implant. The third embodiment forms a liner in the trench before an isotropic etch of the substrate through the trench.
摘要翻译：本发明描述了形成球形STI沟槽的方法的三个实施例。第一实施例开始于在衬底上形成阻挡层。在阻挡层中形成隔离开口。接下来，通过所述隔离开口将离子注入到所述衬底中，以形成Si损伤或掺杂的第一区域。第一区域是选择性蚀刻以形成孔。孔用绝缘材料填充以形成气球形的浅沟槽隔离（STI）区域。衬底在所述球形浅沟槽隔离（STI）区域之间具有有效区域。第二实施例通过在植入物之前在衬底中形成沟槽而与第一实施例不同。在通过沟槽对衬底进行各向同性蚀刻之前，第三实施例在沟槽中形成衬垫。

17. 发明授权

US06297109B1 Method to form shallow junction transistors while eliminating shorts due to junction spiking 失效
标题翻译：形成浅结晶体管的方法，同时消除由于接头尖峰引起的短路
公开(公告)号：US06297109B1
公开(公告)日：2001-10-02
申请号：US09377543
申请日：1999-08-19
申请人： Lap Chan , Cher Liang Cha , Ravishankar Sundaresan
发明人： Lap Chan , Cher Liang Cha , Ravishankar Sundaresan
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/28044 , H01L29/41775 , H01L29/41783 , H01L29/456 , H01L29/4916 , H01L29/4941 , H01L29/665 , H01L29/66545
摘要： A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions. The second electrode layer is etched through to form separate conductive connections. An intermetal dielectric layer is deposited. The intermetal dielectric layer is etched through to form contact openings. A metal layer is deposited and etched through to form separate metal interconnects. A passivation layer is deposited, and the integrated circuit is completed.
摘要翻译：实现了形成浅结MOSFET的方法。栅极氧化层形成在衬底上。沉积多晶硅或金属的第一电极层。沉积氮化硅层。氮化硅层和第一电极层被蚀刻通过以形成临时MOSFET栅极。将离子注入到衬底中以形成轻掺杂的结。沉积间隔层。间隔层和栅极氧化物层被各向异性地蚀刻以形成侧壁间隔物。将离子注入到衬底中以形成重掺杂的结。蚀刻掉氮化硅层。多晶硅或金属的第二电极层沉积在衬底，侧壁间隔物和第一多晶硅层上。将第二电极层抛光到侧壁间隔物的顶表面以完成MOSFET并形成永久栅极和与源极和漏极结的导电连接。蚀刻第二电极层以形成分开的导电连接。沉积金属间电介质层。金属间电介质层被蚀刻穿过以形成接触开口。金属层被沉积并蚀刻通过以形成单独的金属互连。沉积钝化层，并且集成电路完成。

18. 发明授权

US06284610B1 Method to reduce compressive stress in the silicon substrate during silicidation 失效
标题翻译：降低硅衬底中压缩应力的方法
公开(公告)号：US06284610B1
公开(公告)日：2001-09-04
申请号：US09666315
申请日：2000-09-21
申请人： Randall Cher Liang Cha , Chee Tee Chua , Kin Leong Pey , Lap Chan
发明人： Randall Cher Liang Cha , Chee Tee Chua , Kin Leong Pey , Lap Chan
IPC分类号： H01L21336
CPC分类号： H01L29/66628 , H01L29/41775 , H01L29/41783 , H01L29/665 , H01L29/7845
摘要： A method for siliciding source/drain junctions is described wherein compressive stress of the underlying silicon is avoided by the insertion of a buffer layer between the silicide and the silicon. A gate electrode and associated source/drain extensions are provided in and on a semiconductor substrate. A buffer oxide layer is deposited overlying the semiconductor substrate and the gate electrode. A polysilicon layer is deposited overlying the buffer oxide layer. The polysilicon layer will form the source/drain junctions and silicon source. The source/drain junctions are silicided whereby the buffer oxide layer provides compressive stress relief during the siliciding.
摘要翻译：描述了用于硅化源极/漏极结的方法，其中通过在硅化物和硅之间插入缓冲层来避免下面的硅的压缩应力。栅极电极和相关的源极/漏极延伸部设置在半导体衬底中和半导体衬底上。沉积在半导体衬底和栅电极上的缓冲氧化层。堆叠在缓冲氧化物层上的多晶硅层。多晶硅层将形成源极/漏极结和硅源。源极/漏极结是硅化的，由此缓冲氧化物层在硅化期间提供压缩应力释放。

19. 发明授权

US06252290B1 Method to form, and structure of, a dual damascene interconnect device 有权
标题翻译：双镶嵌互连装置的形成和结构的方法
公开(公告)号：US06252290B1
公开(公告)日：2001-06-26
申请号：US09425903
申请日：1999-10-25
申请人： Shyue Fong Quek , Ting Cheong Ang , Lap Chan , Sang Yee Loong
发明人： Shyue Fong Quek , Ting Cheong Ang , Lap Chan , Sang Yee Loong
IPC分类号： H01L2900
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76835 , H01L2221/1026
摘要： A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprises the following steps. A first level via photo sensitive dielectric layer is deposited and exposed over a semiconductor structure. A first level trench photo sensitive dielectric layer is deposited and exposed over the first via photo sensitive dielectric layer. The exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers are patterned and etched to form a first level dual damascene opening. The first level dual damascene opening comprises an integral first level via and metal line openings. A first level metal layer is deposited over the first level trench photo sensitive dielectric layer, filling the first level dual damascene opening. The first level metal layer is planarized to form at least one first level dual damascene interconnect having a first level horizontal metal line and a first level vertical via stack. The above steps are repeated n-1 times to form n-1 more dual damascene interconnects over the first level dual damascene interconnect where n is the number of interconnect levels desired. A passivation layer is deposited and patterned over the nth metal dual damascene interconnect layer to form openings in the passivation layer. The n number of via photo sensitive dielectric and trench photo sensitive dielectric layers are stripped and removed beneath the passivation layer openings and between the plurality of dual damascene structures wherein the portion of the via photo sensitive dielectric underneath the horizontal metal lines of the stripped trench photo sensitive dielectric layers remains.
摘要翻译：一种在半导体器件中制造双镶嵌互连结构的方法，包括以下步骤。通过光敏电介质层的第一级沉积并暴露在半导体结构上。第一级沟槽光电介质层被沉积并暴露在第一通孔光敏介电层上。通过光敏电介质和沟槽光敏电介质层曝光的第一级被图案化和蚀刻以形成第一级双镶嵌开口。第一级双镶嵌开口包括集成的第一级通孔和金属线开口。第一级金属层沉积在第一级沟槽光敏介电层上，填充第一级双镶嵌开口。第一级金属层被平坦化以形成具有第一级水平金属线和第一级垂直通孔叠层的至少一个第一级双镶嵌互连。上述步骤重复n-1次，以在第一级双镶嵌互连上形成n-1个双镶嵌互连，其中n是所需的互连级数。在第n个金属双镶嵌互连层上沉积并图案化钝化层，以在钝化层中形成开口。在钝化层开口之下和多个双镶嵌结构之间剥离并除去n个通孔光敏电介质层和沟槽光敏介电层，其中通过光敏电介质的部分在剥离的沟槽照片的水平金属线下方保持敏感的电介质层。

20. 发明授权

US06180501B2 Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process 失效
标题翻译：制造二分之一微米自对准钛硅化物工艺的双多晶硅栅极结构的方法
公开(公告)号：US06180501B2
公开(公告)日：2001-01-30
申请号：US09418036
申请日：1999-10-14
申请人： Kin-Leong Pey , Chaw Sing Ho , Lap Chan
发明人： Kin-Leong Pey , Chaw Sing Ho , Lap Chan
IPC分类号： H01L213205
CPC分类号： H01L29/6659 , H01L21/28035 , H01L21/28052 , H01L21/28518 , H01L29/4925 , H01L29/4933 , H01L29/66545
摘要： This invention relates to the fabrication of integrated circuit devices and more particularly to a method for minimizing the localized mechanical stress problems that can occur when silicided polysilicon gates are used to fabricate narrow channel CMOS devices. The invention addresses the avoidance of typical stress-induced problems in polysilicon gates, such as non-uniform silicide (including bowing, thinning edges, etc.) and voids, which are becoming increasingly worse as gate lengths continue to be reduced. The key to this invention is to spread the highly detrimental mechanical stresses, in narrow silicided gates, over a larger vertical surface area. This is accomplished by using a thin/thick double polysilicon stack for the gate, whereby, the lower thin polysilicon gate layer is not silicided and the upper thick polysilicon layer is subsequently silicided. An insulating layer is used to prevent silicidation of the lower thin polysilicon gate, during silicidation of active source-drain regions. The same insulating layer is also used to avoid another cause of mechanical stress, by protecting the surface grain boundaries of the lower thin polysilicon gate layer from being stuffed with polymer during the dry etching used for spacer formation. The tall stacked gate structure allows the silicide-induced stresses to be more safely located farther away from the active devices.
摘要翻译：本发明涉及集成电路器件的制造，更具体地说，涉及一种使硅化多晶硅栅极用于制造窄沟道CMOS器件时可能出现的局部机械应力问题最小化的方法。本发明解决了避免多晶硅栅极中的典型的应力引起的问题，例如不均匀的硅化物（包括弯曲，变薄边缘等）和空隙，随着栅极长度的不断减小，这些问题变得越来越严重。本发明的关键是在狭窄的硅化物栅极中，在较大的垂直表面积上传播高度有害的机械应力。这是通过使用用于栅极的薄/厚双重多晶硅堆叠实现的，由此，下部薄多晶硅栅极层不被硅化，并且随后硅化上部厚多晶硅层。在有源源极 - 漏极区域的硅化期间，使用绝缘层来防止下部薄多晶硅栅极的硅化。同样的绝缘层也用于通过在用于间隔物形成的干蚀刻期间保护下部薄多晶硅栅极层的表面晶界不被聚合物填充而避免机械应力的另一个原因。高堆叠栅极结构允许硅化物引起的应力更安全地远离有源器件。

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