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    • 12. 发明授权
    • Enhancing timeliness of cache prefetching
    • 提高缓存预取的及时性
    • US08285941B2
    • 2012-10-09
    • US12036476
    • 2008-02-25
    • Kattamuri EkanadhamJennifer A. NavarroIl ParkChung-Lung Kevin Shum
    • Kattamuri EkanadhamJennifer A. NavarroIl ParkChung-Lung Kevin Shum
    • G06F12/06
    • G06F12/0862G06F2212/6026
    • A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.
    • 提供了一种用于增强处理系统中的高速缓存存储器预取的及时性的系统,方法和计算机程序产品。 系统包括步幅图案检测器,用于检测作为连续高速缓存访​​问之间的差异的字节量的步幅大小的步幅图案。 系统还包括置信柜台。 该系统还包括用于当步幅大小小于高速缓存行大小时执行方法的迫切预取控制逻辑。 该方法包括响应于步幅模式检测器检测步幅模式来调整置信计数器,将置信计数器与置信阈值进行比较,以及响应于达到置信阈值的置信度计数器请求高速缓存预取。 系统还可以包括选择逻辑以在急切预取控制逻辑和标准步幅预取控制逻辑之间进行选择。
    • 13. 发明授权
    • Event tracking hardware
    • 事件跟踪硬件
    • US08140761B2
    • 2012-03-20
    • US12630946
    • 2009-12-04
    • Kattamuri EkanadhamIl Park
    • Kattamuri EkanadhamIl Park
    • G06F12/00
    • G06F12/0897G06F11/348G06F12/0875G06F2201/88
    • An event tracking hardware engine having N (≧2) caches is invoked when an event of interest occurs, using a corresponding key. The event tracking engine stores a cumulative number of occurrences for each one of the different kinds of events, and searches in the N caches for an entry for the key. When an entry for the key is found, the engine increments the number of occurrences if no overflow of the cumulative number of occurrences would occur. However, if the incrementing would cause overflow, then instead of incrementing the cumulative number of occurrences, the engine promotes the entry for the event of interest to a next higher cache.
    • 使用对应的密钥,当感兴趣的事件发生时,调用具有N(≥2)个高速缓存的事件跟踪硬件引擎。 事件跟踪引擎存储每种不同类型事件的累积发生次数,并在N个高速缓存中搜索密钥的条目。 当找到密钥的条目时,如果没有发生累计发生次数的溢出,引擎会增加出现次数。 然而,如果增量会导致溢出,那么引擎不会增加累积的出现次数,而是为下一个更高的缓存感兴趣的事件提升条目。
    • 14. 发明授权
    • Prefetching indirect array accesses
    • 预取间接数组访问
    • US07539844B1
    • 2009-05-26
    • US12144952
    • 2008-06-24
    • Kattamuri EkanadhamIl ParkSeetharami R. Seelam
    • Kattamuri EkanadhamIl ParkSeetharami R. Seelam
    • G06F12/00
    • G06F12/0862G06F2212/6024
    • A method for prefetching data from an array, A, the method including: detecting a stride, dB, of a stream of index addresses of an indirect array, B, contents of each index address having information for determining an address of an element of the array A; detecting an access pattern from the indirect array, B, to data in the array, A, wherein the detecting an access pattern includes: using a constant value of an element size, dA; using a domain size k; executing a load instruction to load bi at address, ia, and receiving index data, mbi; multiplying mbi by dA to produce the product mbi*dA; executing another load instruction to load for a column address, j, where 1≦j≦k, and receiving address aj; recording the difference, aj−mbi*dA; iterating the executing a load instruction, the multiplying, the executing another load instruction, and the recording to produce another difference; incrementing a counter by one if the difference and the another difference are the same; and confirming column address j when the counter reaches a pre-determined threshold; executing a load instruction to load bi+dB and receiving index data nextmbi; and executing a load instruction to load Aj+nextmbi*dA, where Aj=(aj−mbi*dA) when the column address j is confirmed to prefetch the data from the array, A.
    • 一种用于从阵列预取数据的方法A,所述方法包括:检测间接阵列的索引地址流的步幅,dB,每个索引地址的内容具有用于确定所述数据的元素的地址的信息 阵列A; 检测来自间接阵列B的访问模式到数组A中的数据,其中检测访问模式包括:使用元素大小的常数值dA; 使用域大小k; 执行加载指令以在地址加载bi,ia和接收索引数据mbi; 将mbi乘以dA以产生乘积mbi * dA; 执行另一个加载指令以加载列地址j,其中1 <= j <= k,并接收地址aj; 记录差异,aj-mbi * dA; 迭代执行加载指令,乘法,执行另一加载指令和记录以产生另一差异; 如果差异和另一个差异相同,则将计数器递增1; 以及当所述计数器达到预定阈值时确认列地址j; 执行加载指令以加载bi + dB并接收索引数据nextmbi; 并且当确定列地址j从数组中预取数据时,执行加载指令以加载Aj + nextmbi * dA,其中Aj =(aj-mbi * dA)。
    • 16. 发明授权
    • Method of maintaining data coherency in a computer system having a
plurality of interconnected nodes
    • 在具有多个互连节点的计算机系统中维护数据一致性的方法
    • US06085295A
    • 2000-07-04
    • US954496
    • 1997-10-20
    • Kattamuri EkanadhamBeng-Hong LimPratap Chandra PattnaikMarc Snir
    • Kattamuri EkanadhamBeng-Hong LimPratap Chandra PattnaikMarc Snir
    • G06F12/08G06F12/16
    • G06F12/0813G06F12/0817G06F2212/2542
    • A method of providing coherent shared memory access among a plurality of shared memory multiprocessor nodes. For each line of data in each of the nodes, a list of those processors of the node that have copies of the line in their caches is maintained. If a memory command is issued from a processor of one node, and if the command is directed to a line of memory of another node, then the memory command is sent directly to an adapter of the one node. When the adapter receives the command, it forwards the command from the one adapter to another adapter of the other node. When the other adapter receives the command, the command is forwarded to the local memory of the other node. The list of processors is then updated in the local memory of the other node to include or exclude the other adapter depending on the command. If the memory command is issued from one of the processors of one of the nodes, and if the command is directed to a line of memory of the one node, then the command is sent directly to local memory. When the local memory receives the command and if the adapter of the node is in the list of processors for a line associated with the command and if the command is a write command, then the command is forwarded to the adapter of the one node. When the adapter receives the command, the command is forwarded to remote adapters in each of the remote nodes which have processors which have cache copies of the line. Finally, when the latter remote adapters receive the command, the command is forwarded to the processors having the cache copies of the line.
    • 一种在多个共享存储器多处理器节点之间提供一致的共享存储器访问的方法。 对于每个节点中的每一行数据,维护节点中具有其高速缓存中的行的副本的那些处理器的列表。 如果从一个节点的处理器发出存储器命令,并且如果命令被定向到另一个节点的存储器行,则存储器命令被直接发送到该一个节点的适配器。 当适配器接收到命令时,它将该命令从一个适配器转发到另一个节点的另一个适配器。 当另一个适配器接收到该命令时,该命令将转发到另一个节点的本地内存。 然后在另一个节点的本地存储器中更新处理器列表,以根据命令包括或排除另一个适配器。 如果从其中一个节点的一个处理器发出存储器命令,并且如果命令被定向到一个节点的存储器行,则该命令被直接发送到本地存储器。 当本地内存接收到该命令时,如果节点的适配器位于与该命令相关联的一行的处理器列表中,并且该命令是写入命令,则该命令将转发到该一个节点的适配器。 当适配器接收到该命令时,该命令将转发到具有具有该行的高速缓存副本的处理器的每个远程节点中的远程适配器。 最后,当后一个远程适配器接收到该命令时,该命令被转发到具有该行的缓存副本的处理器。