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1. 发明授权

US06085295A Method of maintaining data coherency in a computer system having a plurality of interconnected nodes 失效
标题翻译：在具有多个互连节点的计算机系统中维护数据一致性的方法
公开(公告)号：US06085295A
公开(公告)日：2000-07-04
申请号：US954496
申请日：1997-10-20
申请人： Kattamuri Ekanadham , Beng-Hong Lim , Pratap Chandra Pattnaik , Marc Snir
发明人： Kattamuri Ekanadham , Beng-Hong Lim , Pratap Chandra Pattnaik , Marc Snir
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F12/0813 , G06F12/0817 , G06F2212/2542
摘要： A method of providing coherent shared memory access among a plurality of shared memory multiprocessor nodes. For each line of data in each of the nodes, a list of those processors of the node that have copies of the line in their caches is maintained. If a memory command is issued from a processor of one node, and if the command is directed to a line of memory of another node, then the memory command is sent directly to an adapter of the one node. When the adapter receives the command, it forwards the command from the one adapter to another adapter of the other node. When the other adapter receives the command, the command is forwarded to the local memory of the other node. The list of processors is then updated in the local memory of the other node to include or exclude the other adapter depending on the command. If the memory command is issued from one of the processors of one of the nodes, and if the command is directed to a line of memory of the one node, then the command is sent directly to local memory. When the local memory receives the command and if the adapter of the node is in the list of processors for a line associated with the command and if the command is a write command, then the command is forwarded to the adapter of the one node. When the adapter receives the command, the command is forwarded to remote adapters in each of the remote nodes which have processors which have cache copies of the line. Finally, when the latter remote adapters receive the command, the command is forwarded to the processors having the cache copies of the line.
摘要翻译：一种在多个共享存储器多处理器节点之间提供一致的共享存储器访问的方法。对于每个节点中的每一行数据，维护节点中具有其高速缓存中的行的副本的那些处理器的列表。如果从一个节点的处理器发出存储器命令，并且如果命令被定向到另一个节点的存储器行，则存储器命令被直接发送到该一个节点的适配器。当适配器接收到命令时，它将该命令从一个适配器转发到另一个节点的另一个适配器。当另一个适配器接收到该命令时，该命令将转发到另一个节点的本地内存。然后在另一个节点的本地存储器中更新处理器列表，以根据命令包括或排除另一个适配器。如果从其中一个节点的一个处理器发出存储器命令，并且如果命令被定向到一个节点的存储器行，则该命令被直接发送到本地存储器。当本地内存接收到该命令时，如果节点的适配器位于与该命令相关联的一行的处理器列表中，并且该命令是写入命令，则该命令将转发到该一个节点的适配器。当适配器接收到该命令时，该命令将转发到具有具有该行的高速缓存副本的处理器的每个远程节点中的远程适配器。最后，当后一个远程适配器接收到该命令时，该命令被转发到具有该行的缓存副本的处理器。

2. 发明授权

US5802582A Explicit coherence using split-phase controls 失效
标题翻译：使用分相控制的显式一致性
公开(公告)号：US5802582A
公开(公告)日：1998-09-01
申请号：US711750
申请日：1996-09-10
申请人： Kattamuri Ekanadham , Beng-Hong Lim , Pratap Chandra Pattnaik
发明人： Kattamuri Ekanadham , Beng-Hong Lim , Pratap Chandra Pattnaik
IPC分类号： G06F9/46 , G06F12/08 , G06F15/177 , G06F12/14
CPC分类号： G06F9/52 , G06F12/0815
摘要： A method and apparatus for maintaining cache coherence in a shared memory multiprocessor system, where cache coherence is preserved between lock acquires and releases rather than at every single memory load and store. With this invention, a Global Lock Manager (GLM) keeps track of the status of locked ranges without the need to maintain a list of individual processors in the system. Further a Recently Acquired Lock Manager (RALM) keeps track of the status of locked ranges within a processing node to reduce the need to communicate with a GLM.
摘要翻译：一种用于在共享存储器多处理器系统中维持高速缓存一致性的方法和装置，其中在锁获取和释放之间保存高速缓存一致性，而不是在每个单个存储器加载和存储期间。利用本发明，全球锁管理器（GLM）跟踪锁定范围的状态，而不需要维护系统中的各个处理器的列表。另外，最近获得的锁管理器（RALM）跟踪处理节点内锁定范围的状态，以减少与GLM进行通信的需要。

3. 发明授权

US5893922A Home node migration for distributed shared memory systems 失效
标题翻译：分布式共享内存系统的家庭节点迁移
公开(公告)号：US5893922A
公开(公告)日：1999-04-13
申请号：US813814
申请日：1997-03-06
申请人： Sandra Johnson Baylor , Kattamuri Ekanadham , Joefon Jann , Beng-Hong Lim , Pratap Chandra Pattnaik
发明人： Sandra Johnson Baylor , Kattamuri Ekanadham , Joefon Jann , Beng-Hong Lim , Pratap Chandra Pattnaik
IPC分类号： G06F9/50 , G06F12/08 , G06F13/00
CPC分类号： G06F9/5016 , G06F12/0813
摘要： A mechanism to dynamically migrate a home node of a global page to a more suitable node for improving performance of parallel applications running on a S-COMA and other DSM systems. More specifically, consultation counts are maintained at each client node of a shared memory system, where the consultation count indicates the number of times the client node has consulted the dynamic for lines a page. This information is then used along with other information to decide on whether to change the dynamic home node to a more suitable node.
摘要翻译：将全局页面的家庭节点动态迁移到更合适的节点以提高在S-COMA和其他DSM系统上运行的并行应用程序的性能的机制。更具体地，在共享存储器系统的每个客户端节点处维护咨询计数，其中咨询计数指示客户端节点已经查阅了页面的行的动态次数。然后将该信息与其他信息一起使用以决定是否将动态家庭节点更改为更合适的节点。

4. 发明授权

US07107399B2 Scalable memory 失效
标题翻译：可扩展内存
公开(公告)号：US07107399B2
公开(公告)日：2006-09-12
申请号：US09854213
申请日：2001-05-11
申请人： Gianfranco Bilardi , Kattamuri Ekanadham , Pratap Chandra Pattnaik
发明人： Gianfranco Bilardi , Kattamuri Ekanadham , Pratap Chandra Pattnaik
IPC分类号： G06F12/00
CPC分类号： G11C7/1057 , G06F12/08 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A memory structure and method for handling memory requests from a processor and for returning correspondence responses to the processor from various levels of the memory structure. The memory levels of the memory structure are interconnected by a forward and return path with the return path having twice the bandwidth of the forward path. An algorithm is used to determine how many responses are sent from each memory level on the return path to the processor. This algorithm is designed to guarantee a constant bound on the rate of responses sent to the processor. More specifically, if a write request is at the same level to which it is targeted, or if a request at a memory level is targeted to a higher memory level, then two responses are forwarded from a controller at the memory level on the return path to the processor. Otherwise, only one response is forwarded from the memory level on the return path.
摘要翻译：一种用于处理来自处理器的存储器请求并用于从存储器结构的各个级别返回到处理器的对应响应的存储器结构和方法。存储器结构的存储器级别通过前向和返回路径互连，返回路径具有正向路径的两倍的带宽。一种算法用于确定从返回路径上的每个存储器级别发送到处理器的响应数量。该算法旨在保证对发送到处理器的响应速率的恒定限制。更具体地说，如果写入请求处于与其所针对的相同级别，或者如果存储器级别的请求针对更高的存储器级别，则在返回路径上的存储器级的控制器处转发两个响应到处理器。否则，只有一个响应从返回路径上的内存级别转发。

5. 发明申请

US20080282059A1 METHOD AND APPARATUS FOR DETERMINING MEMBERSHIP IN A SET OF ITEMS IN A COMPUTER SYSTEM 审中-公开
标题翻译：用于在计算机系统中确定一组项目中的会员的方法和装置
公开(公告)号：US20080282059A1
公开(公告)日：2008-11-13
申请号：US11746269
申请日：2007-05-09
申请人： Kattamuri Ekanadham , Il Park , Pratap Chandra Pattnaik , Xiaowei Shen
发明人： Kattamuri Ekanadham , Il Park , Pratap Chandra Pattnaik , Xiaowei Shen
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3855
摘要： A method and apparatus for maintaining membership in a set of items to be used in a predetermined manner in a computer system. A representation of each member of the set is mapped into a number of components of a primary and secondary vector when a member is added to the set. Periodically, the primary vector is changed to the secondary vector and the secondary vector to the primary vector. When members of the set are deleted, the components of the secondary vector are changed to indicate deletion of these members after the primary vector is changed to the secondary vector. Finally, membership in the set is determined by examining the components in the primary vector, and the members in the set of items are then used in a predetermined manner in the computer system. More specifically, in a sample embodiment of the present invention, membership in the set would determine if data is to be stored or removed from cache memory in a computer system. This invention, for example, provides a low cost and high performance mechanism to phase out aging membership information in a prefeteching mechanism for caching data or instructions in a computer system.
摘要翻译：一种用于在计算机系统中以预定方式使用的一组项目中的成员资格维护的方法和装置。当成员添加到集合中时，集合的每个成员的表示形式映射到主要和次要向量的多个组件。周期地，主向量被改变为次矢量，次矢量变为主矢量。当组的成员被删除时，次要向量的组件被改变以指示在将主向量改变为次要向量之后删除这些成员。最后，通过检查主向量中的组件来确定组中的成员资格，然后在计算机系统中以预定的方式使用该组项中的成员。更具体地说，在本发明的一个示例实施例中，该集合的成员资格将确定数据是否要在计算机系统中的高速缓存存储器中被存储或移除。例如，本发明提供了一种低成本和高性能的机制，用于在用于在计算机系统中缓存数据或指令的预取机制中逐步淘汰老化成员资格信息。

6. 发明授权

US06978360B2 Scalable processor 失效
标题翻译：可扩展处理器
公开(公告)号：US06978360B2
公开(公告)日：2005-12-20
申请号：US09854243
申请日：2001-05-11
申请人： Gianfranco Bilardi , Kattamuri Ekanadham , Pratap Chandra Pattnaik
发明人： Gianfranco Bilardi , Kattamuri Ekanadham , Pratap Chandra Pattnaik
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/383 , G06F9/3834 , G06F9/3885
摘要： A method and apparatus for issuing and executing memory instructions from a computer system so as to (1) maximize the number of requests issued to a highly pipe-lined memory, the only limitation being data dependencies in the program and (2) avoid reading data from memory before a corresponding write to memory. The memory instructions are organized to read and write into memory, by using explicit move instructions, thereby avoiding any data storage limitations in the processor. The memory requests are organized to carry complete information, so that they can be processed independently when memory returns the requested data. The memory is divided into a number of regions, each of which is associated with a fence counter. The fence counter for a memory region is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.
摘要翻译：一种用于从计算机系统发出和执行存储器指令的方法和装置，以便（1）最大限度地发送给高度管道内存的请求数量，唯一的限制是程序中的数据依赖性，以及（2）避免读取数据从内存之前对相应的写入内存。存储器指令通过使用显式移动指令被组织以读取和写入存储器，从而避免了处理器中的任何数据存储限制。存储器请求被组织以携带完整的信息，使得当存储器返回所请求的数据时它们可以被独立地处理。存储器被分成多个区域，每个区域与栅栏计数器相关联。每当存储区域的存储器指令被发出并且每次对存储器区域进行写操作时，存储器区域的栅栏计数器递增。发出栅栏指令后，如果栅栏指令中指定的存储器区域的计数器高于阈值，则不会再发出存储指令。当执行足够数量的未完成的发出的指令时，计数器将递减到阈值以下，然后再发出存储器指令。

7. 发明授权

US5745781A Memoryless communications adapter including queueing and matching primitives for scalable distributed parallel computer systems 失效
标题翻译：无记忆通信适配器，包括用于可扩展分布式并行计算机系统的排队和匹配原语
公开(公告)号：US5745781A
公开(公告)日：1998-04-28
申请号：US598931
申请日：1996-02-09
申请人： Kattamuri Ekanadham , Hubertus Franke , Douglas James Joseph , Pratap Pattnaik , Marc Snir
发明人： Kattamuri Ekanadham , Hubertus Franke , Douglas James Joseph , Pratap Pattnaik , Marc Snir
IPC分类号： G06F15/173 , G06F3/00
CPC分类号： G06F15/17381
摘要： A memoryless communications adapter for communicating between the nodes of a distributed parallel computer network, each node including a non-shared program memory coupled to the memoryless communications adapter which interfaces the network. An embodiment of the present invention advantageously provides an adapter that can manipulate queues and matching tables efficiently in hardware and provide a high-level object view of queues and matching in the context of communication between nodes. Preferably, the Queue manipulation logic, Match Table manipulation logic and the Sequence Table manipulation logic are implemented in the adapter hardware which does not keep any state or resources in it that depend on the size of the system or the number of queues/tables instantiated. The actual states of these objects may be kept in the program memory, so that the adapter hardware is memoryless.
摘要翻译：一种用于在分布式并行计算机网络的节点之间进行通信的无记忆通信适配器，每个节点包括耦合到接口网络的无记忆通信适配器的非共享程序存储器。本发明的实施例有利地提供了一种适配器，其可以在硬件中有效地操纵队列和匹配表，并且在节点之间的通信的上下文中提供队列的高级对象视图和匹配。优选地，队列操作逻辑，匹配表操作逻辑和序列表操作逻辑在适配器硬件中实现，该适配器硬件不保持依赖于系统的大小或实例化的队列/表的数量的任何状态或资源。这些对象的实际状态可以保存在程序存储器中，以便适配器硬件是无记忆的。

8. 发明申请

US20110314259A1 OPERATING A STACK OF INFORMATION IN AN INFORMATION HANDLING SYSTEM 有权
标题翻译：在信息处理系统中操作信息堆栈
公开(公告)号：US20110314259A1
公开(公告)日：2011-12-22
申请号：US12817609
申请日：2010-06-17
申请人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , IL Park
发明人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , IL Park
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30134 , G06F9/30163 , G06F9/3861
摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.
摘要翻译：一个指针用于指向一堆信息中的下一个读取位置。将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

9. 发明申请

US20100287536A1 PROFILING APPLICATION PERFORMANCE ACCORDING TO DATA STRUCTURE 失效
标题翻译：根据数据结构分析应用性能
公开(公告)号：US20100287536A1
公开(公告)日：2010-11-11
申请号：US12436894
申请日：2009-05-07
申请人： I-Hsin Chung , Guojing Cong , Kattamuri Ekanadham , David Klepacki , Simone Sbaraglia , Hui-Fang Wen
发明人： I-Hsin Chung , Guojing Cong , Kattamuri Ekanadham , David Klepacki , Simone Sbaraglia , Hui-Fang Wen
IPC分类号： G06F11/36 , G06F9/44 , G06F9/45
CPC分类号： G06F8/443 , G06F11/3471 , G06F2201/865
摘要： During runtime of a binary program file, streams of instructions are executed and memory references, generated by instrumentation applied to given ones of the instructions that refer to memory locations, are collected. A transformation is performed, based on the executed streams of instructions and the collected memory references, to obtain a table. The table lists memory events of interest for active data structures for each function in the program file. The transformation is performed to translate memory addresses for given ones of the instructions and given ones of the data structures into locations and variable names in a source file corresponding to the binary file. At least the memory events of interest are displayed, and the display is organized so as to correlate the memory events of interest with corresponding ones of the data structures.
摘要翻译：在二进制程序文件的运行期间，执行指令流，并且收集通过应用于指向存储器位置的给定指令的仪器产生的存储器引用。基于所执行的指令流和所收集的存储器引用执行变换以获得表。该表列出了程序文件中每个功能的活动数据结构感兴趣的内存事件。执行转换以将给定的指令的内存地址转换为与二进制文件相对应的源文件中的数据结构中的位置和变量名。至少显示感兴趣的存储器事件，并且显示被组织以使感兴趣的存储器事件与相应的数据结构相关联。

10. 发明授权

US5408658A Self-scheduling parallel computer system and method 失效
标题翻译：自调并行计算机系统及方法
公开(公告)号：US5408658A
公开(公告)日：1995-04-18
申请号：US730365
申请日：1991-07-15
申请人： Rudolph N. Rechtschaffen , Kattamuri Ekanadham
发明人： Rudolph N. Rechtschaffen , Kattamuri Ekanadham
IPC分类号： G06F9/38 , G06F9/45 , G06F15/16
CPC分类号： G06F9/3808 , G06F8/451 , G06F9/3802 , G06F9/3812 , G06F9/3836 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： An incremental method is described for distributing the instructions of an execution sequence among a plurality of processing elements for execution in parallel. The distribution is based upon anticipated availability times of the needed input values for each instruction as well as the anticipated availability times of each processing element for handling each instruction. A self-parallelizing computer system and method are also described for asynchronously processing the distributed instructions in two modes of execution on a set of processing elements which communicate with each other.
摘要翻译：描述了用于在多个处理元件之间并行执行执行序列的指令的分发方法。该分配基于每个指令的所需输入值的预期可用时间以及用于处理每个指令的每个处理元件的预期可用时间。还描述了一种自并行计算机系统和方法，用于在一组彼此通信的处理元件上以两种执行模式异步处理分布式指令。

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