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11. 发明申请

US20080297213A1 Signaling with Superimposed Clock and Data Signals 失效
标题翻译：信号与叠加的时钟和数据信号
公开(公告)号：US20080297213A1
公开(公告)日：2008-12-04
申请号：US12128584
申请日：2008-05-28
申请人： Aliazam Abbasfar , Amir Amirkhany , Bruno W. Garlepp
发明人： Aliazam Abbasfar , Amir Amirkhany , Bruno W. Garlepp
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/07 , H03L7/087 , H04L7/0008 , H04L7/0025 , H04L7/033
摘要： A data receiver circuit includes an interface to receive an input signal that includes a data signal and a clock signal superimposed on the data signal. The data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate. The clock signal has a frequency N times the associated symbol rate, where N is an integer. A phase-locked loop (PLL) coupled to the interface extracts the clock signal from the input signal to provide an extracted clock signal. A phase interpolator adjusts the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal. A sampling circuit samples the data signal at a sampling point. The sampling circuit is synchronized to the phase-adjusted extracted clock signal.
摘要翻译：数据接收器电路包括接收包括数据信号和叠加在数据信号上的时钟信号的输入信号的接口。数据信号具有相关联的符号率和相关联的符号周期等于相关联符号率的倒数。时钟信号具有相关符号率N倍的频率，其中N是整数。耦合到接口的锁相环（PLL）从输入信号提取时钟信号以提供提取的时钟信号。相位内插器调整提取的时钟信号的相位以提供相位调整的提取的时钟信号。采样电路在采样点采样数据信号。采样电路与相位调整的提取时钟信号同步。

12. 发明授权

US08149972B2 Signaling with superimposed clock and data signals 失效
标题翻译：信号叠加时钟和数据信号
公开(公告)号：US08149972B2
公开(公告)日：2012-04-03
申请号：US12128584
申请日：2008-05-28
申请人： Aliazam Abbasfar , Amir Amirkhany , Bruno W. Garlepp
发明人： Aliazam Abbasfar , Amir Amirkhany , Bruno W. Garlepp
IPC分类号： H04L7/00
CPC分类号： H03L7/085 , H03L7/07 , H03L7/087 , H04L7/0008 , H04L7/0025 , H04L7/033
摘要： A data receiver circuit includes an interface to receive an input signal that includes a data signal and a clock signal superimposed on the data signal. The data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate. The clock signal has a frequency N times the associated symbol rate, where N is an integer. A phase-locked loop (PLL) coupled to the interface extracts the clock signal from the input signal to provide an extracted clock signal. A phase interpolator adjusts the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal. A sampling circuit samples the data signal at a sampling point. The sampling circuit is synchronized to the phase-adjusted extracted clock signal.
摘要翻译：数据接收器电路包括接收包括数据信号和叠加在数据信号上的时钟信号的输入信号的接口。数据信号具有相关联的符号率和相关联的符号周期等于相关联符号率的倒数。时钟信号具有相关符号率N倍的频率，其中N是整数。耦合到接口的锁相环（PLL）从输入信号提取时钟信号以提供提取的时钟信号。相位内插器调整提取的时钟信号的相位以提供相位调整的提取的时钟信号。采样电路在采样点采样数据信号。采样电路与相位调整的提取时钟信号同步。

13. 发明授权

US08031802B2 Multi-channel signaling with equalization 失效
标题翻译：具有均衡的多信道信令
公开(公告)号：US08031802B2
公开(公告)日：2011-10-04
申请号：US12515390
申请日：2007-11-09
申请人： Aliazam Abbasfar , Amir Amirkhany
发明人： Aliazam Abbasfar , Amir Amirkhany
IPC分类号： H04L27/00
CPC分类号： H04L25/03343 , H04L5/0007 , H04L5/06 , H04L25/03057 , H04L27/2637 , H04L27/2644 , H04L2025/03414 , H04L2025/03426 , H04L2025/0349
摘要： A data transmission circuit comprises a plurality of data preparation circuits and a combiner. Each data preparation circuit receives a respective data stream and generates a respective sub-channel signal. Each respective data stream has a respective symbol rate and a respective Nyquist bandwidth. The combiner combines the respective sub-channel signals to generate a data transmission signal having an associated bandwidth. The bandwidth associated with the data transmission signal is greater than or equal to the sum of the Nyquist bandwidths for the respective data streams. Each data preparation circuit comprises a programmable linear equalizer that equalizes the respective sub-channel signal across the bandwidth of the data transmission signal.
摘要翻译：数据传输电路包括多个数据准备电路和组合器。每个数据准备电路接收相应的数据流并产生相应的子信道信号。每个相应的数据流具有相应的符号率和相应的奈奎斯特带宽。组合器组合各个子信道信号以产生具有相关带宽的数据传输信号。与数据传输信号相关联的带宽大于或等于相应数据流的奈奎斯特带宽的总和。每个数据准备电路包括一个可编程线性均衡器，用于跨数据传输信号的带宽均衡相应的子信道信号。

14. 发明申请

US20110228864A1 RESONANCE MITIGATION FOR HIGH-SPEED SIGNALING 有权
标题翻译：高速信号共振减速
公开(公告)号：US20110228864A1
公开(公告)日：2011-09-22
申请号：US13129998
申请日：2009-12-03
申请人： Farshid Aryanfar , Aliazam Abbasfar , Amir Amirkhany
发明人： Farshid Aryanfar , Aliazam Abbasfar , Amir Amirkhany
IPC分类号： H04L27/00
CPC分类号： H04L25/0272 , H04L25/03878
摘要： The frequency response of a first component signal path of a differential signaling link is adjusted to off-set a notch in the frequency response from a corresponding notch in the frequency response of a second component signal path of the differential signaling link.
摘要翻译：差分信号链路的第一分量信号路径的频率响应被调整为在差分信令链路的第二分量信号路径的频率响应中的对应的陷波中使得频率响应中的陷波偏移。

15. 发明授权

US07925686B2 Linear transformation circuit 失效
标题翻译：线性变换电路
公开(公告)号：US07925686B2
公开(公告)日：2011-04-12
申请号：US11311971
申请日：2005-12-19
申请人： Aliazam Abbasfar , Amir Amirkhany , Vladimir Stojanovic , Mark A. Horowitz
发明人： Aliazam Abbasfar , Amir Amirkhany , Vladimir Stojanovic , Mark A. Horowitz
IPC分类号： G06F17/14 , G06F17/15
CPC分类号： G06J1/00
摘要： A first device is described. The first device may include a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit may have an input to receive a vector having N digital values and an output to output N first output signals, a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H, and a conversion (DAC) circuit coupled to the sign-adjustment circuit. Outputs from the DAC circuit may be summed to produce an output.
摘要翻译：描述第一设备。第一装置可以包括线性变换电路以实现矩阵D的乘法。线性变换电路可以具有用于接收具有N个数字值的矢量的输入和用于输出N个第一输出信号的输出，用于调整的符号调整电路根据一组系数H包括至少N个N个第一输出信号的子集的符号，以及耦合到符号调整电路的转换（DAC）电路。来自DAC电路的输出可以相加以产生输出。

16. 发明申请

US20080310491A1 MULTI-MODE TRANSMITTER 失效
标题翻译：多模发射机
公开(公告)号：US20080310491A1
公开(公告)日：2008-12-18
申请号：US12117680
申请日：2008-05-08
申请人： Aliazam Abbasfar , Amir Amirkhany
发明人： Aliazam Abbasfar , Amir Amirkhany
IPC分类号： H04L27/01 , H04L27/00
CPC分类号： H04L27/0008
摘要： A multi-mode transmitter within an integrated circuit device. The multi-mode transmitter transmits a first data sequence in a baseband signal when a first transmission mode is enabled, and transmits the first data sequence in a multi-band signal when a second transmission mode is enabled.
摘要翻译：集成电路设备内的多模发射机。当第一传输模式被使能时，多模式发射机发送基带信号中的第一数据序列，并且当启用第二传输模式时，将多个第一数据序列发送到多频带信号。

17. 发明申请

US20070143387A1 Linear transformation circuit 失效
标题翻译：线性变换电路
公开(公告)号：US20070143387A1
公开(公告)日：2007-06-21
申请号：US11311971
申请日：2005-12-19
申请人： Aliazam Abbasfar , Amir Amirkhany , Vladimir Stojanovic , Mark Horowitz
发明人： Aliazam Abbasfar , Amir Amirkhany , Vladimir Stojanovic , Mark Horowitz
IPC分类号： G06F17/14
CPC分类号： G06J1/00
摘要： A first device is described. The first device may include a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit may have an input to receive a vector having N digital values and an output to output N first output signals, a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H, and a conversion (DAC) circuit coupled to the sign-adjustment circuit. Outputs from the DAC circuit may be summed to produce an output.
摘要翻译：描述第一设备。第一装置可以包括线性变换电路以实现矩阵D的乘法。线性变换电路可以具有用于接收具有N个数字值的矢量的输入和用于输出N个第一输出信号的输出，用于调整的符号调整电路根据一组系数H包括至少N个N个第一输出信号的子集的符号，以及耦合到符号调整电路的转换（DAC）电路。来自DAC电路的输出可以相加以产生输出。

18. 发明申请

US20130063191A1 Methods and Circuits for Duty-Cycle Correction 审中-公开
标题翻译：用于周期校正的方法和电路
公开(公告)号：US20130063191A1
公开(公告)日：2013-03-14
申请号：US13612540
申请日：2012-09-12
申请人： Dinesh Patil , Mohammad Hekmat , Kambiz Kaviani , Amir Amirkhany
发明人： Dinesh Patil , Mohammad Hekmat , Kambiz Kaviani , Amir Amirkhany
IPC分类号： H03K3/017 , H03L7/08
CPC分类号： H03L7/0812 , H03K5/1565
摘要： A duty-cycle correction circuit calibrates the duty cycle of a periodic input signal. The correction circuit includes a state machine that samples the input signal using a sample signal of a sample period. The sample period is selected to scan a period of the input signal over a number of sample periods. The resultant difference between the number of high and low samples provides a measure of the duty cycle deviation from e.g. 50%. An adjustable delay circuit adjusts the relative timing of the rising and falling edges of the input signal, and thus the duty cycle, responsive to the measure of duty cycle.
摘要翻译：占空比校正电路校准周期性输入信号的占空比。校正电路包括使用采样周期的采样信号对输入信号进行采样的状态机。选择采样周期以在多个采样周期上扫描输入信号的周期。所得到的高和低样本数之间的差异提供了与例如数据的占空比偏差的度量。 50％。可调节延迟电路调整输入信号的上升沿和下降沿的相对定时，从而根据占空比的测量来调整占空比。

19. 发明授权

US08531206B2 High resolution output driver 有权
标题翻译：高分辨率输出驱动
公开(公告)号：US08531206B2
公开(公告)日：2013-09-10
申请号：US13391383
申请日：2010-09-14
申请人： Amir Amirkhany , Chaofeng Huang , Kambiz Kaviani , Wayne D. Dettloff , Kun-Yung Chang
发明人： Amir Amirkhany , Chaofeng Huang , Kambiz Kaviani , Wayne D. Dettloff , Kun-Yung Chang
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K19/017581 , H03M1/1061 , H03M1/745 , H04L25/0278 , H04L25/0288 , H04L25/03343
摘要： High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.
摘要翻译：具有相对较少数量的子驱动器分支或切片的高分辨率输出驱动器，每个子驱动器分支或切片具有显着大于量化步长的标称阻抗，并且通过显着小于量化步长的阻抗步长递增地彼此不同。在一个实现中，这种“差分”或“不均匀”子驱动器切片实现n选择k均衡器的相应元件，每个这样的差分子驱动器切片由均匀元件阻抗校准DAC实现。在另一实施方式中，均匀分片均衡器的每个分量由差分片阻抗校准DAC实现，并且在又一实现中，差分片均衡器的每个分量由差分片阻抗校准DAC实现。在一组额外的实施方案中，均衡和阻抗校准功能在各个并行的驱动器分支组中实现，而不是分层实现中嵌套的“DAC内的DAC”布置。通过这种双边安排，避免了均衡器和校准器量化的乘法，从而降低了满足指定范围和分辨率所需的副驱动器片的总数。

20. 发明申请

US20120147944A1 HIGH RESOLUTION OUTPUT DRIVER 有权
标题翻译：高分辨率输出驱动器
公开(公告)号：US20120147944A1
公开(公告)日：2012-06-14
申请号：US13391383
申请日：2010-09-14
申请人： Amir Amirkhany , Chaofeng Huang , Kambiz Kaviani , Wayne D. Dettloof , Kun-Yung Chang
发明人： Amir Amirkhany , Chaofeng Huang , Kambiz Kaviani , Wayne D. Dettloof , Kun-Yung Chang
IPC分类号： H04L27/01
CPC分类号： H03K19/0005 , H03K19/017581 , H03M1/1061 , H03M1/745 , H04L25/0278 , H04L25/0288 , H04L25/03343
摘要： High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.
摘要翻译：具有相对较少数量的子驱动器分支或切片的高分辨率输出驱动器，每个子驱动器分支或切片具有显着大于量化步长的标称阻抗，并且通过显着小于量化步长的阻抗步长递增地彼此不同。在一个实现中，这种“差分”或“不均匀”子驱动器切片实现n选择k均衡器的相应元件，每个这样的差分子驱动器切片由均匀元件阻抗校准DAC实现。在另一实施方式中，均匀分片均衡器的每个分量由差分片阻抗校准DAC实现，并且在又一实现中，差分片均衡器的每个分量由差分片阻抗校准DAC实现。在一组额外的实施方案中，均衡和阻抗校准功能在各个并行的驱动器分支组中实现，而不是分层实现中嵌套的“DAC内的DAC”布置。通过这种双边安排，避免了均衡器和校准器量化的乘法，从而降低了满足指定范围和分辨率所需的副驱动器片的总数。

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