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11. 发明授权

US07183154B2 Nonvolatile memory cells having split gate structure and methods of fabricating the same 有权
公开(公告)号：US07183154B2
公开(公告)日：2007-02-27
申请号：US10980992
申请日：2004-11-04
申请人： Jin-Woo Kim , Dong-Jun Kim , Min-Soo Cho , Dai-Geun Kim
发明人： Jin-Woo Kim , Dong-Jun Kim , Min-Soo Cho , Dai-Geun Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/11556 , H01L27/115
摘要： Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.

12. 发明申请

US20060272300A1 Dust receptacle fixing/separating apparatus and a cyclone dust collecting device having the same 有权
公开(公告)号：US20060272300A1
公开(公告)日：2006-12-07
申请号：US11317549
申请日：2005-12-23
申请人： Dong-Jun Kim , Kyoung-Woung Kim
发明人： Dong-Jun Kim , Kyoung-Woung Kim
IPC分类号： B01D46/00
CPC分类号： A47L9/1683 , Y10S55/03
摘要： Disclosed are a dust receptacle fixing/separating apparatus that fixes and separates a dust receptacle with respect to a cyclone unit, and a cyclone dust collecting device having the same. The dust receptacle fixing/separating apparatus comprises a fixing/separating handle, a locking/unlocking part, and a fixing part. The fixing/separating handle pivots between a first position and a second position, the first position in which the cyclone unit and the dust receptacle are fixed to each other and the second position in which the cyclone unit and the dust receptacle can be separated from each other. The locking/unlocking part fixes and releases the fixing/separating handle when the fixing/separating handle is in the first position. The fixing part pivotably mounting the fixing/separating handle releases connection between the cyclone unit and the dust receptacle when the fixing/separating handle is in the second position.

13. 发明授权

US06730565B2 Method of forming flash memory 失效
标题翻译：形成闪存的方法
公开(公告)号：US06730565B2
公开(公告)日：2004-05-04
申请号：US10277848
申请日：2002-10-22
申请人： Min-Soo Cho , Dong-Jun Kim , Jin-Woo Kim
发明人： Min-Soo Cho , Dong-Jun Kim , Jin-Woo Kim
IPC分类号： H10L21336
CPC分类号： H01L27/11519 , H01L21/28273 , H01L27/115 , H01L27/11521
摘要： The present invention provides a method of forming a split gate type flash memory. After exposure of a floating gate layer between silicon nitride layers, a conductive layer spacer is formed on a sidewall of the silicon nitride layer pattern. The conductive layer spacer is formed in a floating gate of a later-completed flash memory to form a tip on which tunneling is centralized in an erase operation. That is, the spacer is formed on a sidewall of the silicon nitride layer pattern over the floating gate layer to form the tunneling tip.
摘要翻译：本发明提供一种形成分离式闪存的方法。在氮化硅层之间的浮栅层暴露之后，在氮化硅层图案的侧壁上形成导电层间隔物。导电层隔离物形成在随后完成的闪速存储器的浮动栅极中，以形成在擦除操作中将隧道集中在其上的尖端。也就是说，间隔物形成在浮动栅极层上的氮化硅层图案的侧壁上以形成隧道末端。

14. 发明授权

US5936887A Non-volatile memory device with NAND type cell structure 失效
标题翻译：具有NAND型单元结构的非易失性存储器件
公开(公告)号：US5936887A
公开(公告)日：1999-08-10
申请号：US910025
申请日：1997-08-12
申请人： Jung-Dal Choi , Dong-Jun Kim , Wang-Chul Shin , Jong-Han Kim
发明人： Jung-Dal Choi , Dong-Jun Kim , Wang-Chul Shin , Jong-Han Kim
IPC分类号： H01L21/8247 , G11C11/56 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/115 , G11C11/5621 , G11C16/0483 , H01L27/11521 , G11C16/24 , G11C2211/5649 , G11C7/18
摘要： A non-volatile memory device is disclosed in which a pair of two adjacent memory cell strings are commonly connected to one bit line and the memory cell strings are selectively driven to obtain a relatively wide pitch margin between two bit lines. The device has a conductive plate line which is located along each memory cell string or a pair of memory cell strings to drive memory cells thereof with a relatively low program voltage to a word line. The memory device comprises a plurality of memory cell strings which are arranged in parallel with one another and each of which extends in the same direction as a bit line 12, and a pair of two adjacent memory cell strings 11a and 11b are commonly connected to the bit line 12. The memory device also comprises a string selector for selecting either the first string 11a or the second string 11b in response to signals from string select lines SSL1 and SSL2, and a plurality of plate lines PLa or 21a and PLb or 21b which are respectively arranged on the first and second strings 11a and 11b. In the memory cell, if voltages having different levels are applied to the control gate of a memory cell of the string selected thus and the plate line, at least more than two coupling voltages are induced to a floating gate of a corresponding memory cell so that two bits of information can be stored in and read out of one memory cell. The memory device has a cell structure in which a pair of two adjacent memory cell strings are commonly connected to one bit line, so that margin width between two bit lines, i.e., a bit line pitch can be relatively widely obtained.
摘要翻译：公开了一种非易失性存储器件，其中一对两个相邻的存储器单元串共同连接到一个位线，并且存储器单元串被选择性地驱动以在两个位线之间获得相对较宽的间距余量。该装置具有沿着每个存储单元串或一对存储单元串定位的导电板线，以将具有相对低的编程电压的存储单元驱动到字线。存储器件包括彼此并联布置的多个存储单元串，并且每个存储单元串沿与位线12相同的方向延伸，并且一对两个相邻的存储单元串11a和11b共同连接到存储装置还包括用于响应于来自串选择线SSL1和SSL2的信号以及多个板线PLa或21a和PLb或21b而选择第一串11a或第二串11b的串选择器，其中分别布置在第一和第二弦11a和11b上。在存储单元中，如果将具有不同电平的电压施加到由此选择的串的存储单元的控制栅极和板线，则至少两个耦合电压被感应到相应存储单元的浮动栅极，使得两位信息可以存储在一个存储单元中并从其中读出。存储器件具有单元结构，其中一对两个相邻的存储单元串共同连接到一个位线，使得可以相对广泛地获得两个位线之间的裕度宽度，即位线间距。

15. 发明授权

US5734609A Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure and methods of operating same 失效
标题翻译：具有降低对无意编程和擦除的敏感性的集成电路存储器件及其操作方法
公开(公告)号：US5734609A
公开(公告)日：1998-03-31
申请号：US757266
申请日：1996-11-29
申请人： Jung-dal Choi , Dong-Jun Kim
发明人： Jung-dal Choi , Dong-Jun Kim
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C16/0483
摘要： Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure include an array of memory cells arranged as a plurality of NAND strings of EEPROM cells which share common control lines (e.g., SSL1, SSL2) and word lines (e.g., WL1-WLn). These NAND strings preferably comprise a linear array or chain of EEPROM cells having first and second ends and first and second select transistors (ST1, ST2) coupled (directly or indirectly) to (he first and second ends, respectively. To provide improved program and erase capability, a pair of NAND strings are provided in antiparallel and share a common bit line. However, the pair of NAND strings are formed in respective nonoverlapping well regions in a substrate so that the channel regions of the EEPROM cells in respective NAND strings can be individually controlled (e.g., raised) to prevent inadvertent programming or erasing when cells in adjacent strings are being programmed or erased, respectively.
摘要翻译：具有降低的对无意编程和擦除的敏感性的集成电路存储器件包括布置成共享共同控制线（例如，SSL1，SSL2）和字线（例如，WL1-WLn）的多个EEPROM单元的NAND串的存储器单元的阵列，。这些NAND串优选地包括具有第一和第二端的线性阵列或EEPROM单元串，以及分别连接（直接或间接）到其第一和第二端的第一和第二选择晶体管（ST1，ST2），以提供改进的程序和擦除能力，反并联提供一对NAND串并共享一个公共位线，但是这对NAND串形成在衬底中的各个非重叠阱区中，使得各个NAND串中的EEPROM单元的沟道区可以分别控制（例如，升高）以防止在相邻串中的单元被编程或擦除时意外编程或擦除。

16. 发明申请

US20060145233A1 Method of fabricating a semiconductor device capacitor having a dielectric barrier layer and a semiconductor device capacitor having the same 审中-公开
标题翻译：制造具有电介质阻挡层的半导体器件电容器及其半导体器件电容器的方法
公开(公告)号：US20060145233A1
公开(公告)日：2006-07-06
申请号：US11320385
申请日：2005-12-28
申请人： Kyong-Min Kim , Dong-Jun Kim , Kwang-Woon Lee
发明人： Kyong-Min Kim , Dong-Jun Kim , Kwang-Woon Lee
IPC分类号： H01L29/00 , H01L21/36
CPC分类号： H01L28/56 , H01L27/10852 , H01L28/57
摘要： A method of forming a capacitor of a semiconductor device is provided. In the method, a capacitor lower electrode is deposited on a semiconductor substrate and then a dielectric layer is deposited on the lower electrode. A dielectric barrier layer is deposited on an upper part of the dielectric layer. The dielectric barrier layer comprises a material for preventing degradation of a leakage current characteristic of the dielectric layer. The method further comprises depositing a capacitor upper electrode on an upper part of the dielectric barrier layer.
摘要翻译：提供一种形成半导体器件的电容器的方法。在该方法中，在半导体衬底上沉积电容器下电极，然后在下部电极上沉积电介质层。介电阻挡层沉积在电介质层的上部。电介质阻挡层包括用于防止介电层的漏电流特性劣化的材料。该方法还包括在电介质阻挡层的上部上沉积电容器上电极。

17. 发明申请

US20050064655A1 Nonvolatile memory cells having split gate structure and methods of fabricating the same 有权
公开(公告)号：US20050064655A1
公开(公告)日：2005-03-24
申请号：US10980992
申请日：2004-11-04
申请人： Jin-Woo Kim , Dong-Jun Kim , Min-Soo Cho , Dai-Geun Kim
发明人： Jin-Woo Kim , Dong-Jun Kim , Min-Soo Cho , Dai-Geun Kim
IPC分类号： G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/8238
CPC分类号： H01L27/11556 , H01L27/115
摘要： Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.

18. 发明授权

US06867082B2 Nonvolatile memory cells having split gate structure and methods of fabricating the same 失效
标题翻译：具有分裂栅极结构的非易失性存储单元及其制造方法
公开(公告)号：US06867082B2
公开(公告)日：2005-03-15
申请号：US10844240
申请日：2004-05-12
申请人： Jin-Woo Kim , Dong-Jun Kim , Min-Soo Cho , Dai-Geun Kim
发明人： Jin-Woo Kim , Dong-Jun Kim , Min-Soo Cho , Dai-Geun Kim
IPC分类号： G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/8238
CPC分类号： H01L27/11556 , H01L27/115
摘要： Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.
摘要翻译：提供具有分裂栅极结构的非易失性存储单元及其制造方法。非易失性存储单元包括限定在半导体衬底的预定区域的有源区。每个有源区的一部分被蚀刻以形成单元沟槽区。绝缘浮动栅极设置在与穿过有源区域的方向平行的一对侧壁上。源区域设置在单元沟槽区域的底表面处。浮置栅极之间的间隙区填充有与源极区域电连接的公共源极线。公共源极线沿着与有源区域交叉的方向延伸。与浮动栅极相邻的有源区域被与公共源极线平行的字线覆盖。漏极区域设置在与字线相邻的有源区域中。漏极区域电连接到跨越字线的位线。

19. 发明授权

US06784476B2 Semiconductor device having a flash memory cell and fabrication method thereof 有权
标题翻译：具有闪存单元的半导体器件及其制造方法
公开(公告)号：US06784476B2
公开(公告)日：2004-08-31
申请号：US10039126
申请日：2002-01-03
申请人： Dong-Jun Kim , Jin-Ho Kim , Yong-Kyu Lee , Min-Soo Cho , Eui-Youl Ryu
发明人： Dong-Jun Kim , Jin-Ho Kim , Yong-Kyu Lee , Min-Soo Cho , Eui-Youl Ryu
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328
摘要： In a non-volatile semiconductor memory device and a fabrication method thereof, a charge storage layer is formed on a substrate. A control gate layer is formed on the charge storage layer. A gate mask having a spacer-shape is formed on the control gate layer. The charge storage layer and the control gate layer are removed using the gate mask as protection to form a control gate and a charge storage region.
摘要翻译：在非易失性半导体存储器件及其制造方法中，在基板上形成电荷存储层。在电荷存储层上形成控制栅极层。在控制栅极层上形成具有间隔物形状的栅极掩模。使用栅极掩模去除电荷存储层和控制栅极层作为保护以形成控制栅极和电荷存储区域。

20. 发明授权

US06753571B2 Nonvolatile memory cells having split gate structure and methods of fabricating the same 失效
标题翻译：具有分裂栅极结构的非易失性存储单元及其制造方法
公开(公告)号：US06753571B2
公开(公告)日：2004-06-22
申请号：US10401666
申请日：2003-03-28
申请人： Jin-Woo Kim , Dong-Jun Kim , Min-Soo Cho , Dai-Geun Kim
发明人： Jin-Woo Kim , Dong-Jun Kim , Min-Soo Cho , Dai-Geun Kim
IPC分类号： H01L29788
CPC分类号： H01L27/11556 , H01L27/115
摘要： Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.
摘要翻译：提供具有分裂栅极结构的非易失性存储单元及其制造方法。非易失性存储单元包括限定在半导体衬底的预定区域的有源区。每个有源区的一部分被蚀刻以形成单元沟槽区。绝缘浮动栅极设置在与穿过有源区域的方向平行的一对侧壁上。源区域设置在单元沟槽区域的底表面处。浮置栅极之间的间隙区填充有与源极区域电连接的公共源极线。公共源极线沿着与有源区域交叉的方向延伸。与浮动栅极相邻的有源区域用与公共源极线平行的字线覆盖。漏极区域设置在与字线相邻的有源区域中。漏极区域电连接到跨越字线的位线。

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