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1. 发明授权

US06784476B2 Semiconductor device having a flash memory cell and fabrication method thereof 有权
标题翻译：具有闪存单元的半导体器件及其制造方法
公开(公告)号：US06784476B2
公开(公告)日：2004-08-31
申请号：US10039126
申请日：2002-01-03
申请人： Dong-Jun Kim , Jin-Ho Kim , Yong-Kyu Lee , Min-Soo Cho , Eui-Youl Ryu
发明人： Dong-Jun Kim , Jin-Ho Kim , Yong-Kyu Lee , Min-Soo Cho , Eui-Youl Ryu
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328
摘要： In a non-volatile semiconductor memory device and a fabrication method thereof, a charge storage layer is formed on a substrate. A control gate layer is formed on the charge storage layer. A gate mask having a spacer-shape is formed on the control gate layer. The charge storage layer and the control gate layer are removed using the gate mask as protection to form a control gate and a charge storage region.
摘要翻译：在非易失性半导体存储器件及其制造方法中，在基板上形成电荷存储层。在电荷存储层上形成控制栅极层。在控制栅极层上形成具有间隔物形状的栅极掩模。使用栅极掩模去除电荷存储层和控制栅极层作为保护以形成控制栅极和电荷存储区域。

2. 发明授权

US06724661B2 Erasing method in non-volatile memory device 有权
标题翻译：非易失性存储器件中的擦除方法
公开(公告)号：US06724661B2
公开(公告)日：2004-04-20
申请号：US10090902
申请日：2002-05-31
申请人： Yong-Kyu Lee , Dong-Jun Kim , Min-Soo Cho , Eui-Youl Ryu , Jin-Ho Kim
发明人： Yong-Kyu Lee , Dong-Jun Kim , Min-Soo Cho , Eui-Youl Ryu , Jin-Ho Kim
IPC分类号： G11C1604
CPC分类号： G11C16/14
摘要： A method for performing an erase operation in a memory cell. A first voltage and a second voltage are applied to the source and drain regions, respectively, for a predetermined erase time; and the first and second voltages are switched with each other between the source and drain regions at least one time for the erase time. Thereby, hole is easily injected to the source and drain regions and a channel lateral surface, and a uniform and high-speed erase operation is archived.
摘要翻译：一种在存储单元中执行擦除操作的方法。分别在源极和漏极区域施加第一电压和第二电压达预定的擦除时间; 并且第一和第二电压在源极和漏极区之间彼此切换至少一次以用于擦除时间。因此，孔容易地注入到源极和漏极区域以及沟道横向表面，并且存储均匀且高速的擦除操作。

3. 发明授权

US06803276B2 Semiconductor device having a flash memory cell and fabrication method thereof 有权
公开(公告)号：US06803276B2
公开(公告)日：2004-10-12
申请号：US10616391
申请日：2003-07-09
申请人： Dong-Jun Kim , Jin-Ho Kim , Yong-Kyu Lee , Min-Soo Cho , Eui-Youl Ryu
发明人： Dong-Jun Kim , Jin-Ho Kim , Yong-Kyu Lee , Min-Soo Cho , Eui-Youl Ryu
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328
摘要： In a non-volatile semiconductor memory device and a fabrication method thereof, a charge storage layer is formed on a substrate. A control gate layer is formed on the charge storage layer. A gate mask having a spacer-shape is formed on the control gate layer. The charge storage layer and the control gate layer are removed using the gate mask as protection to form a control gate and a charge storage region.

4. 发明授权

US06924542B2 Trench isolation without grooving 有权
公开(公告)号：US06924542B2
公开(公告)日：2005-08-02
申请号：US10901948
申请日：2004-07-29
申请人： Hua Ji , Dong Jun Kim , Jin-Ho Kim , Chuck Jang
发明人： Hua Ji , Dong Jun Kim , Jin-Ho Kim , Chuck Jang
IPC分类号： H01L21/762 , H01L29/00 , H01L21/8238
CPC分类号： H01L21/76229
摘要： A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.

5. 发明授权

US06787409B2 Method of forming trench isolation without grooving 有权
标题翻译：无沟槽形成沟槽隔离的方法
公开(公告)号：US06787409B2
公开(公告)日：2004-09-07
申请号：US10305464
申请日：2002-11-26
申请人： Hua Ji , Dong Jun Kim , Jin-Ho Kim , Chuck Jang
发明人： Hua Ji , Dong Jun Kim , Jin-Ho Kim , Chuck Jang
IPC分类号： H01L218238
CPC分类号： H01L21/76229
摘要： A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.
摘要翻译：提供了一种形成没有沟槽氧化物开槽的浅沟槽隔离区的方法和结构。特别地，一种方法包括两步氧化法，其中氧化物衬垫在沟槽的内表面上划线，并且沟槽填充有本体氧化物层，优选使用高密度等离子体化学气相沉积（HDP-CVD）工艺。氧化物衬垫和本体氧化物层被形成为具有相似的蚀刻速率。因此，当在堆叠结构之间蚀刻氧化物衬垫和本体氧化物层时，形成基本平坦且没有凹槽的公共电介质顶表面。

6. 发明授权

US08785992B2 Light-guiding structure, image sensor including the light-guiding structure, and processor-based system including the image sensor 有权
标题翻译：导光结构，包括导光结构的图像传感器和包括图像传感器的基于处理器的系统
公开(公告)号：US08785992B2
公开(公告)日：2014-07-22
申请号：US13186667
申请日：2011-07-20
申请人： Kang-Hyun Baek , Sang-Il Jung , Jin-Ho Kim , Jeong-Ho Lee , Jeong-Bin Kim
发明人： Kang-Hyun Baek , Sang-Il Jung , Jin-Ho Kim , Jeong-Ho Lee , Jeong-Bin Kim
IPC分类号： H01L31/062 , H01L31/113 , H01L27/146
CPC分类号： H01L27/14629
摘要： An example embodiment relates to a light-guiding structure. The light-guiding structure may include a bottom surface and a sidewall defined by a first, a second, and a third insulating layer disposed on a semiconductor substrate. The bottom surface may be parallel to a main surface of the semiconductor substrate and may be disposed in the first insulating layer. The sidewall may penetrate the second and third insulating layers to extend to the first insulating layer, and the sidewall may be tapered with respect to the main surface of semiconductor substrate. The light-guiding structure may be included in a image sensor. The image sensor may be included in a processor-based system.
摘要翻译：示例性实施例涉及导光结构。导光结构可以包括由设置在半导体衬底上的第一，第二和第三绝缘层限定的底表面和侧壁。底表面可以平行于半导体衬底的主表面并且可以设置在第一绝缘层中。侧壁可以穿透第二和第三绝缘层以延伸到第一绝缘层，并且侧壁可以相对于半导体衬底的主表面是锥形的。导光结构可以包括在图像传感器中。图像传感器可以包括在基于处理器的系统中。

7. 发明授权

US08674494B2 Semiconductor package having supporting plate and method of forming the same 有权
标题翻译：具有支撑板的半导体封装及其形成方法
公开(公告)号：US08674494B2
公开(公告)日：2014-03-18
申请号：US13564309
申请日：2012-08-01
申请人： Tae-Duk Nam , Jin-Ho Kim , Hyuk-Su Kim , Hyoung-Suk Kim , Tae-Young Lee
发明人： Tae-Duk Nam , Jin-Ho Kim , Hyuk-Su Kim , Hyoung-Suk Kim , Tae-Young Lee
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/3128 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/18 , H01L25/50 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16265 , H01L2224/291 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/32265 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2924/01013 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19105 , H01L2924/014 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging substrate. The support plate may be spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging substrate. A second semiconductor chip may be provided on the first semiconductor chip and on the support plate so that the first semiconductor chip is between the second semiconductor chip and the packaging substrate and so that the support plate is between the second semiconductor chip and the packaging substrate. An adhesion layer may bond the second semiconductor chip to the first semiconductor chip and may bond the second semiconductor chip to the support plate. In addition, an electrical coupling may be provided between the first semiconductor chip and the packaging substrate.
摘要翻译：半导体封装可以包括封装衬底，封装衬底上的第一半导体芯片，以及封装衬底上的支撑板。支撑板可以在相对于包装基板的表面平行的方向上与第一半导体芯片间隔开。可以在第一半导体芯片和支撑板上设置第二半导体芯片，使得第一半导体芯片在第二半导体芯片和封装基板之间，并且支撑板位于第二半导体芯片和封装基板之间。粘合层可以将第二半导体芯片接合到第一半导体芯片，并且可以将第二半导体芯片接合到支撑板。此外，可以在第一半导体芯片和封装基板之间设置电耦合。

8. 发明授权

US08441604B2 Liquid crystal display having circular shaped protrusions on the common electrode 有权
标题翻译：在公共电极上具有圆形突起的液晶显示器
公开(公告)号：US08441604B2
公开(公告)日：2013-05-14
申请号：US13251790
申请日：2011-10-03
申请人： Youn-Seung Choi , Jin-Ho Kim
发明人： Youn-Seung Choi , Jin-Ho Kim
IPC分类号： G02F1/1343 , G02F1/1337
CPC分类号： G02F1/1393 , G02F1/133707 , G02F1/134309 , G02F2001/134318
摘要： A VA mode LCD device is disclosed, to improve the viewing-angle properties by isotropically compensating for a viewing angle, in which the VA mode LCD device includes first and second substrates; a plurality of gate and data lines formed on the first substrate, and formed perpendicularly to define a plurality of pixel regions. A thin film transistor is formed in each pixel region of the first substrate. A pixel electrode and a common electrode are formed in each pixel of the respective first and second substrates, wherein the pixel and common electrodes generate an electric field. At least one first slit of a curved-stripe shape, such as a circular-stripe shape, is formed in the pixel electrode of the first substrate. At least one second slit is formed in the common electrode of the second substrate. A liquid crystal layer formed between the first and second substrates.
摘要翻译：公开了VA模式LCD装置，以通过各向同性地补偿视角来改善视角特性，其中VA模式LCD装置包括第一和第二基板; 多个栅极和数据线，形成在第一基板上，并垂直形成以限定多个像素区域。在第一衬底的每个像素区域中形成薄膜晶体管。像素电极和公共电极形成在相应的第一和第二基板的每个像素中，其中像素和公共电极产生电场。在第一基板的像素电极中形成至少一个弯曲条形状的第一狭缝，例如圆形条纹形状。在第二基板的公共电极中形成至少一个第二狭缝。形成在第一和第二基板之间的液晶层。

9. 发明授权

US08315219B2 Method for supporting mobility of a mobile node in a multi-hop IP network and a network system therefor 有权
标题翻译：支持移动节点在多跳IP网络及其网络系统中的移动性的方法
公开(公告)号：US08315219B2
公开(公告)日：2012-11-20
申请号：US12702793
申请日：2010-02-09
申请人： Jin-Hyoung Kim , Sun-Gi Kim , Dae-Hyung Kwon , Choong-Seon Hong , Jin-Ho Kim , Byung-Goo Choi , Jihyuk Hgo
发明人： Jin-Hyoung Kim , Sun-Gi Kim , Dae-Hyung Kwon , Choong-Seon Hong , Jin-Ho Kim , Byung-Goo Choi , Jihyuk Hgo
IPC分类号： H04W4/00
CPC分类号： H04W8/06 , H04L63/0892 , H04W80/04 , H04W88/182 , Y02D70/144
摘要： A method is provided for supporting mobility of a Mobile Node (MN) in a multi-hop Internet Protocol (IP) network, in which an MN that has moved from a source Personal Area Network (PAN) to a target PAN, sends a Router Solicitation (RS) message with an option for requesting its profile to a gateway of the target PAN, and receives a Router Advertisement (RA) message from the gateway in response to the RS message. The RA message includes a home prefix of the MN as the requested profile. The method supports mobility of MNs, enables unicast communication, and facilitates efficient use of the network.
摘要翻译：提供了一种用于支持移动节点（MN）在多跳互联网协议（IP）网络中的移动性的方法，其中已经从源个人局域网（PAN）移动到目标PAN的MN发送路由器索引（RS）消息具有用于向目标PAN的网关请求其简档的选项，并且响应于RS消息从网关接收路由器通告（RA）消息。 RA消息包括MN的归属前缀作为请求的简档。该方法支持MN的移动性，实现单播通信，并有助于网络的有效利用。

10. 发明申请

US20120196439A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120196439A1
公开(公告)日：2012-08-02
申请号：US13289107
申请日：2011-11-04
申请人： Kook-Joo KIM , Jin-Ho Kim , Seung-Ki Chae , Pil-Kwon Jun , Sun-Hee Park , Gyoung-Eun Byun
发明人： Kook-Joo KIM , Jin-Ho Kim , Seung-Ki Chae , Pil-Kwon Jun , Sun-Hee Park , Gyoung-Eun Byun
IPC分类号： H01L21/28
CPC分类号： H01L23/522 , H01L21/76829 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a conductive pattern structure of a semiconductor device, a first insulating interlayer is formed on a substrate. A first wiring is formed to pass through the first insulating interlayer. An etch stop layer and a second insulating interlayer are sequentially formed on the first insulating interlayer. A second wiring is formed to pass through the second insulating interlayer and the etch stop layer. A dummy pattern is formed to pass through the second insulating layer and the etch stop layer at the same time as forming the second wiring. The second wiring is electrically connected to the first wiring. The dummy pattern is electrically isolated from the second wiring.
摘要翻译：在形成半导体器件的导电图案结构的方法中，在基板上形成第一绝缘中间层。形成第一布线以通过第一绝缘中间层。在第一绝缘中间层上依次形成蚀刻停止层和第二绝缘中间层。形成第二布线以通过第二绝缘中间层和蚀刻停止层。在形成第二布线的同时，形成虚设图形以通过第二绝缘层和蚀刻停止层。第二布线电连接到第一布线。虚设图案与第二布线电隔离。

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