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1. 发明授权

US5734609A Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure and methods of operating same 失效
标题翻译：具有降低对无意编程和擦除的敏感性的集成电路存储器件及其操作方法
公开(公告)号：US5734609A
公开(公告)日：1998-03-31
申请号：US757266
申请日：1996-11-29
申请人： Jung-dal Choi , Dong-Jun Kim
发明人： Jung-dal Choi , Dong-Jun Kim
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C16/0483
摘要： Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure include an array of memory cells arranged as a plurality of NAND strings of EEPROM cells which share common control lines (e.g., SSL1, SSL2) and word lines (e.g., WL1-WLn). These NAND strings preferably comprise a linear array or chain of EEPROM cells having first and second ends and first and second select transistors (ST1, ST2) coupled (directly or indirectly) to (he first and second ends, respectively. To provide improved program and erase capability, a pair of NAND strings are provided in antiparallel and share a common bit line. However, the pair of NAND strings are formed in respective nonoverlapping well regions in a substrate so that the channel regions of the EEPROM cells in respective NAND strings can be individually controlled (e.g., raised) to prevent inadvertent programming or erasing when cells in adjacent strings are being programmed or erased, respectively.
摘要翻译：具有降低的对无意编程和擦除的敏感性的集成电路存储器件包括布置成共享共同控制线（例如，SSL1，SSL2）和字线（例如，WL1-WLn）的多个EEPROM单元的NAND串的存储器单元的阵列，。这些NAND串优选地包括具有第一和第二端的线性阵列或EEPROM单元串，以及分别连接（直接或间接）到其第一和第二端的第一和第二选择晶体管（ST1，ST2），以提供改进的程序和擦除能力，反并联提供一对NAND串并共享一个公共位线，但是这对NAND串形成在衬底中的各个非重叠阱区中，使得各个NAND串中的EEPROM单元的沟道区可以分别控制（例如，升高）以防止在相邻串中的单元被编程或擦除时意外编程或擦除。

2. 发明授权

US09564435B2 Semiconductor device including FinFETs having different gate structures and method of manufacturing the semiconductor device 有权
标题翻译：包括具有不同栅极结构的FinFET和半导体器件的制造方法的半导体器件
公开(公告)号：US09564435B2
公开(公告)日：2017-02-07
申请号：US14754400
申请日：2015-06-29
申请人： Eun-ae Chung , Jung-dal Choi , Toshiro Nakanishi , Yu-bin Kim , Gab-jin Nam , Dong-kyu Lee , Guangfan Jiao
发明人： Eun-ae Chung , Jung-dal Choi , Toshiro Nakanishi , Yu-bin Kim , Gab-jin Nam , Dong-kyu Lee , Guangfan Jiao
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L27/088 , H01L21/8234
CPC分类号： H01L27/0886 , H01L21/823412 , H01L21/823431 , H01L27/1211
摘要： A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.
摘要翻译：半导体器件包括具有其上包括逻辑器件的逻辑器件区域的衬底，以及在其上邻近逻辑器件区域的包括I / O器件的输入/输出（I / O）器件区域。逻辑器件区域上的第一鳍状场效应晶体管（FinFET）包括从衬底突出的第一半导体鳍片，以及在其上具有第一栅极电介质层和第一栅极电极的三栅极结构。 I / O器件区域上的第二FinFET包括从衬底突出的第二半导体鳍片，以及在其上具有第二栅极介电层和第二栅电极的双栅极结构。第一和第二栅极电介质层具有不同的厚度。还讨论了相关设备和制造方法。

3. 发明申请

US20110233636A1 Semiconductor Memory Device and Method of Manufacturing the Same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110233636A1
公开(公告)日：2011-09-29
申请号：US13050320
申请日：2011-03-17
申请人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
发明人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
IPC分类号： H01L29/78
CPC分类号： H01L21/26586 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory device and a method of manufacturing the non-volatile memory device are disclosed. The non-volatile memory device includes a substrate, at least two gate structures on the substrate, and at least one impurity region in portions of the substrate between the at least two gate structures. The center of the at least one impurity region is horizontally offset from the center of a region between the at least two gate structures.
摘要翻译：公开了非易失性存储器件和制造非易失性存储器件的方法。非易失性存储器件包括衬底，衬底上的至少两个栅极结构，以及在至少两个栅极结构之间的衬底的部分中的至少一个杂质区域。至少一个杂质区域的中心与至少两个栅极结构之间的区域的中心水平偏移。

4. 发明申请

US20100327371A1 Memory device and method of fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20100327371A1
公开(公告)日：2010-12-30
申请号：US12805962
申请日：2010-08-26
申请人： Chang-Hyun Lee , Jung-dal Choi
发明人： Chang-Hyun Lee , Jung-dal Choi
IPC分类号： H01L27/088 , H01L21/8239
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.
摘要翻译：一种非易失性存储器，包括串联的多个存储晶体管，其中在其间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域晶体管是第一类型。第一种类型可以是n型或p型。非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

5. 发明授权

US5877980A Nonvolatile memory device having a program-assist plate 失效
标题翻译：具有程序辅助板的非易失性存储器件
公开(公告)号：US5877980A
公开(公告)日：1999-03-02
申请号：US824483
申请日：1997-03-26
申请人： Kyong-moo Mang , Jung-dal Choi
发明人： Kyong-moo Mang , Jung-dal Choi
IPC分类号： G11C16/04 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11519 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile memory device in which an electrically conductive "program assist plate" is formed over the nonvolatile memory cells. Appropriate voltages are applied to the program assist plate to greatly increase the cell coupling ratio, thereby reducing the program and erase voltages, and increasing the speed of operation. The manufacturing process is simple, and it results in a more planar structure which facilitates subsequent manufacturing processes.
摘要翻译：一种在非易失性存储单元上形成导电“程序辅助板”的非易失性存储器件。对程序辅助板施加适当的电压以大大增加单元耦合比，从而减少编程和擦除电压，并提高操作速度。制造过程简单，并且其导致更平坦的结构，其有助于后续制造工艺。

6. 发明授权

US5671176A Semiconductor memory device including program inhibition capacitors and method for controlling program-disturb of non-selected memory cells 失效
标题翻译：包括程序禁止电容器的半导体存储器件和用于控制未选择的存储器单元的程序干扰的方法
公开(公告)号：US5671176A
公开(公告)日：1997-09-23
申请号：US715077
申请日：1996-09-19
申请人： Dong-soo Jang , Jung-dal Choi
发明人： Dong-soo Jang , Jung-dal Choi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/06
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10
摘要： An integrated circuit memory device includes a plurality of wordlines, a plurality of program inhibition lines, a plurality of serially connected memory cell transistors, and a plurality of program inhibition capacitors. Each of the memory cell transistors includes a gate connected to a respective one of the wordlines. Each of the program inhibition capacitors has a first terminal connected to a source/drain of a respective one of the memory cell transistors, and a second terminal connected to a respective one of the program inhibition lines. Related methods are also disclosed.
摘要翻译：集成电路存储器件包括多个字线，多个编程禁止线，多个串联的存储单元晶体管和多个编程禁止电容器。每个存储单元晶体管包括连接到字线中相应一个的栅极。每个编程禁止电容器具有连接到存储单元晶体管的相应一个的源极/漏极的第一端子和连接到相应的一个编程禁止线路的第二端子。还公开了相关方法。

7. 发明申请

US20160104705A1 SEMICONDUCTOR DEVICE INCLUDING FINFETS HAVING DIFFERENT GATE STRUCTURES AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
标题翻译：包括具有不同门结构的熔体的半导体器件和制造半导体器件的方法
公开(公告)号：US20160104705A1
公开(公告)日：2016-04-14
申请号：US14754400
申请日：2015-06-29
申请人： Eun-ae Chung , Jung-dal Choi , Toshiro Nakanishi , Yu-bin Kim , Gab-jin Nam , Dong-kyu Lee , Guangfan Jiao
发明人： Eun-ae Chung , Jung-dal Choi , Toshiro Nakanishi , Yu-bin Kim , Gab-jin Nam , Dong-kyu Lee , Guangfan Jiao
IPC分类号： H01L27/088 , H01L27/12
CPC分类号： H01L27/0886 , H01L21/823412 , H01L21/823431 , H01L27/1211
摘要： A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.
摘要翻译：半导体器件包括具有其上包括逻辑器件的逻辑器件区域的衬底，以及在其上邻近逻辑器件区域的包括I / O器件的输入/输出（I / O）器件区域。逻辑器件区域上的第一鳍状场效应晶体管（FinFET）包括从衬底突出的第一半导体鳍片，以及在其上具有第一栅极电介质层和第一栅极电极的三栅极结构。 I / O器件区域上的第二FinFET包括从衬底突出的第二半导体鳍片，以及在其上具有第二栅极介电层和第二栅电极的双栅极结构。第一和第二栅极电介质层具有不同的厚度。还讨论了相关设备和制造方法。

8. 发明授权

US08134873B2 Flash memory device and programming/erasing method of the same 有权
标题翻译：闪存设备和编程/擦除方法相同
公开(公告)号：US08134873B2
公开(公告)日：2012-03-13
申请号：US12591428
申请日：2009-11-19
申请人： Dong-uk Choi , Jung-dal Choi , Choong-ho Lee , Sung-hoi Hur , Min-tai Yu
发明人： Dong-uk Choi , Jung-dal Choi , Choong-ho Lee , Sung-hoi Hur , Min-tai Yu
IPC分类号： G11C16/06
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/10
摘要： A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors.
摘要翻译：闪速存储器件包括体区域，在体区域上排列成行的第一至第n个存储单元晶体管，分别连接到第一至第n存储单元晶体管的栅极的第一至第n字线，连接到第一存储单元晶体管，连接到第一虚设单元晶体管的栅极的第一虚拟字线，连接到第一虚设单元晶体管的第一选择晶体管，连接到第一选择晶体管的栅极的第一选择线，控制单元连接到第一选择线，电压控制单元适于在以擦除第一至第n个存储单元晶体管的擦除模式中向第一选择线输出低于施加到体区的电压的电压。

9. 发明申请

US20110084329A1 NON-VOLATILE MEMORY DEVICE 失效
标题翻译：非易失性存储器件
公开(公告)号：US20110084329A1
公开(公告)日：2011-04-14
申请号：US12713736
申请日：2010-02-26
申请人： Jang-hyun YOU , Jin-taek Park , Young-woo Park , Jung-dal Choi
发明人： Jang-hyun YOU , Jin-taek Park , Young-woo Park , Jung-dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11565 , H01L27/11573 , H01L29/4234
摘要： A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulating layer and a first blocking insulating layer, a second blocking insulating layer, and a third blocking insulating layer. The non-volatile memory device further includes a peripheral region gate structure formed in the peripheral region of the semiconductor layer. The peripheral region gate structure includes a first peripheral region insulating layer including a same material as a material included in the tunneling insulating layer and a second peripheral region insulating layer including a same material as a material included in the third blocking insulating layer.
摘要翻译：非易失性存储器件包括包括单元区域和外围区域的半导体层，设置在半导体层的单元区域中的单元区域栅极结构，并且其中单元区域栅极结构包括隧道绝缘层和第一阻挡层绝缘层，第二阻挡绝缘层和第三阻挡绝缘层。非易失性存储器件还包括形成在半导体层的周边区域中的外围区域栅极结构。周边区域栅极结构包括：第一周边区域绝缘层，其包括与包含在隧道绝缘层中的材料相同的材料;以及第二周边区域绝缘层，其包括与包含在第三阻挡绝缘层中的材料相同的材料。

10. 发明申请

US20080135912A1 Memory device and method of fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20080135912A1
公开(公告)日：2008-06-12
申请号：US11976389
申请日：2007-10-24
申请人： Chang-Hyun Lee , Jung-dal Choi
发明人： Chang-Hyun Lee , Jung-dal Choi
IPC分类号： H01L29/788 , H01L21/8247
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.
摘要翻译：一种非易失性存储器，包括串联的多个存储晶体管，其中在其间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域晶体管是第一类型。第一种类型可以是n型或p型。非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

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