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11. 发明申请

US20050133884A1 Electronically programmable antifuse and circuits made therewith 有权
标题翻译：电子可编程反熔丝和由其制成的电路
公开(公告)号：US20050133884A1
公开(公告)日：2005-06-23
申请号：US11051703
申请日：2005-02-04
申请人： John Fifield , Wagdi Abadeer , William Tonti
发明人： John Fifield , Wagdi Abadeer , William Tonti
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

12. 发明申请

US20050122160A1 Method and circuit for compensating for tunneling current 失效
标题翻译：用于补偿隧道电流的方法和电路
公开(公告)号：US20050122160A1
公开(公告)日：2005-06-09
申请号：US10731298
申请日：2003-12-09
申请人： Wagdi Abadeer , Jennifer Appleyard , John Fifield , William Tonti
发明人： Wagdi Abadeer , Jennifer Appleyard , John Fifield , William Tonti
IPC分类号： G05F3/02 , G05F3/24
CPC分类号： G05F3/242
摘要： A method and circuit for tunneling leakage current compensation, the method including: forcing a current of known value through a tunneling current leakage monitor device to provide a voltage signal; and regulating an on-chip power supply of the integrated circuit chip based on the voltage signal.
摘要翻译：一种用于隧道泄漏电流补偿的方法和电路，所述方法包括：通过隧道电流泄漏监测装置强制已知值的电流以提供电压信号; 以及基于所述电压信号来调节所述集成电路芯片的片上电源。

13. 发明申请

US20050073354A1 VOLTAGE DIVIDER FOR INTEGRATED CIRCUITS 失效
标题翻译：用于集成电路的电压分压器
公开(公告)号：US20050073354A1
公开(公告)日：2005-04-07
申请号：US10605466
申请日：2003-10-01
申请人： Wagdi Abadeer , John Fifield , William Tonti
发明人： Wagdi Abadeer , John Fifield , William Tonti
IPC分类号： G11C5/14 , H01L27/08 , H01L27/088 , H02J1/00 , H02M3/00
CPC分类号： G11C5/147 , H01L27/0802 , H01L27/088 , H02M3/00
摘要： A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).
摘要翻译：用于集成电路的分压器，不包括使用电阻器。在一个实施例中，电压节点VDD与串联连接的两个n型晶体管NFET1和NFET2连接。 NFET 1包括源极（12），漏极（14），具有栅极区域A1（未示出）的栅电极（16）和p衬底（18）。 NFET2包括源极（20），漏极（22），具有栅极区域A2（未示出）的栅电极（24）和p衬底（26）。 NFET1的源极（12）和漏极（14）与NFET2的栅电极（24）耦合。 NFET1和NFET2之间的电压差与VDD具有线性关系。结果，通过适当地选择各个晶体管栅电极区域（A1）和（A2）之间的比率，可以在NFET1和NFET2之间划分电压VDD。

14. 发明申请

US20070242548A1 Programmable Semiconductor Device 有权
标题翻译：可编程半导体器件
公开(公告)号：US20070242548A1
公开(公告)日：2007-10-18
申请号：US10552971
申请日：2003-04-30
申请人： William Tonti , Wayne Berry , John Fifield , William Guthrie , Richard Kontra
发明人： William Tonti , Wayne Berry , John Fifield , William Guthrie , Richard Kontra
IPC分类号： G11C17/16 , H01L29/10
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译：可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）基本上比第二端部（12b）更宽，并且金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。

15. 发明申请

US20080050866A1 SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES 有权
标题翻译：在公共基板上集成大面积金属体和平面器件的半导体结构及其形成这样的半导体结构的方法
公开(公告)号：US20080050866A1
公开(公告)日：2008-02-28
申请号：US11927780
申请日：2007-10-30
申请人： Roger Booth , Jack Mandelman , William Tonti
发明人： Roger Booth , Jack Mandelman , William Tonti
IPC分类号： H01L21/336
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.
摘要翻译：通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。

16. 发明申请

US20080029843A1 E-Fuse and Method for Fabricating E-Fuses Integrating Polysilicon Resistor Masks 审中-公开
标题翻译：电子保险丝和电子熔丝的制造方法，集成多晶硅电阻掩模
公开(公告)号：US20080029843A1
公开(公告)日：2008-02-07
申请号：US11873197
申请日：2007-10-16
申请人： Roger Booth , William Hovis , Jack Mandelman , William Tonti
发明人： Roger Booth , William Hovis , Jack Mandelman , William Tonti
IPC分类号： H01L29/41
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An E-fuse and a method for fabricating an E-fuse integrating polysilicon resistor masks, and a design structure on which the subject E-fuse circuit resides are provided. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.
摘要翻译：一种电熔丝和一种用于制造集成多晶硅电阻掩模的电子熔丝的方法，以及设置有被检体E熔丝回路的设计结构。电熔丝包括限定熔丝形状的多晶硅层，其包括阴极，阳极和连接在阴极和阳极硅化物层之间的保险丝颈。硅化物形成在多晶硅层上形成，其中非硅化部分在靠近熔丝颈部的阴极的一部分上延伸。非接触部分基本上防止电流在阴极的硅化物形成区域中流动，在保险丝编程期间在保险丝颈部发生电迁移。非接触部分具有比熔丝颈部的串联电阻显着更低的串联电阻。

17. 发明申请

US20070284669A1 METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING 审中-公开
公开(公告)号：US20070284669A1
公开(公告)日：2007-12-13
申请号：US11838934
申请日：2007-08-15
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/76
CPC分类号： B07C5/344 , G01R31/2831
摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

18. 发明申请

US20070210411A1 Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof 失效
标题翻译：具有位于不同高度的端子部分的电可编程熔丝结构及其制造方法
公开(公告)号：US20070210411A1
公开(公告)日：2007-09-13
申请号：US11372334
申请日：2006-03-09
申请人： William Hovis , Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： William Hovis , Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L21/82 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.
摘要翻译：提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处，并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。第一端子部分和第二端子部分平行于支撑表面定向，而熔丝元件包括垂直于支撑表面定向的部分，并且包括至少一个直角弯曲部，其从第一和第二端子部分中的至少一个过渡到保险丝元件的正交取向部分。

19. 发明申请

US20070205485A1 Programmable anti-fuse structures, methods for fabricating programmable anti-fuse structures, and methods of programming anti-fuse structures 审中-公开
标题翻译：可编程反熔丝结构，制造可编程反熔丝结构的方法以及编程反熔丝结构的方法
公开(公告)号：US20070205485A1
公开(公告)日：2007-09-06
申请号：US11366879
申请日：2006-03-02
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L29/00
CPC分类号： H01L27/1203 , H01L21/84 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： Programmable anti-fuse structures for semiconductor device constructions, fabrication methods for forming anti-fuse structures during semiconductor device fabrication, and programming methods for anti-fuse structures. The programmable anti-fuse structure comprises first and second terminals and an anti-fuse layer electrically coupled with the first and second terminals. An electrically-conductive diffusion layer is disposed between the first terminal and the anti-fuse layer. The diffusion layer inhibits diffusion of conductive material from the first terminal to the anti-fuse layer when the anti-fuse structure is unprogrammed, but permits diffusion of the conductive material when a programming voltage is applied between the first and second terminals during operation. Advantageously, the first terminal may be composed of metal and the anti-fuse layer may be composed of a semiconductor. The methods of fabricating the anti-fuse structure do not require an additional lithographic mask but instead rely on damascene process steps used to fabricate interconnection structures for neighboring active devices.
摘要翻译：用于半导体器件结构的可编程抗熔丝结构，在半导体器件制造期间形成抗熔丝结构的制造方法以及用于抗熔丝结构的编程方法。可编程反熔丝结构包括第一和第二端子以及与第一和第二端子电耦合的抗熔丝层。导电扩散层设置在第一端子和反熔丝层之间。当反熔丝结构未编程时，扩散层抑制导电材料从第一端子到抗熔丝层的扩散，但是当在操作期间在第一和第二端子之间施加编程电压时允许导电材料的扩散。有利地，第一端子可以由金属构成，并且抗熔丝层可以由半导体构成。制造抗熔丝结构的方法不需要额外的光刻掩模，而是依赖用于制造相邻有源器件的互连结构的镶嵌工艺步骤。

20. 发明申请

US20070190740A1 ENHANCED SILICON-ON-INSULATOR (SOI) TRANSISTORS AND METHODS OF MAKING ENHANCED SOI TRANSISTORS 审中-公开
标题翻译：增强型硅绝缘体（SOI）晶体管及其制造增强型SOI晶体管的方法
公开(公告)号：US20070190740A1
公开(公告)日：2007-08-16
申请号：US11733249
申请日：2007-04-10
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L21/76
CPC分类号： H01L29/78687 , H01L21/26533 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/66772 , H01L29/7842 , H01L29/7848 , H01L29/78603
摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.
摘要翻译：提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。

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