专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20050186744A1 MOSFET with decoupled halo before extension 失效
标题翻译：扩展前分离光环的MOSFET
公开(公告)号：US20050186744A1
公开(公告)日：2005-08-25
申请号：US10785895
申请日：2004-02-24
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier, , Carl Radens , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier, , Carl Radens , William Tonti
IPC分类号： H01L21/28 , H01L21/336 , H01L21/425 , H01L21/8234 , H01L29/423
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/42376 , H01L29/66553 , H01L29/6659
摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.
摘要翻译：反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响旨在改变装置的串联电阻。逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

12. 发明申请

US20060249799A1 Concurrent fin-fet and thick body device fabrication 有权
公开(公告)号：US20060249799A1
公开(公告)日：2006-11-09
申请号：US11481120
申请日：2006-07-05
申请人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

13. 发明申请

US20080050866A1 SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES 有权
标题翻译：在公共基板上集成大面积金属体和平面器件的半导体结构及其形成这样的半导体结构的方法
公开(公告)号：US20080050866A1
公开(公告)日：2008-02-28
申请号：US11927780
申请日：2007-10-30
申请人： Roger Booth , Jack Mandelman , William Tonti
发明人： Roger Booth , Jack Mandelman , William Tonti
IPC分类号： H01L21/336
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.
摘要翻译：通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。

14. 发明申请

US20080029843A1 E-Fuse and Method for Fabricating E-Fuses Integrating Polysilicon Resistor Masks 审中-公开
标题翻译：电子保险丝和电子熔丝的制造方法，集成多晶硅电阻掩模
公开(公告)号：US20080029843A1
公开(公告)日：2008-02-07
申请号：US11873197
申请日：2007-10-16
申请人： Roger Booth , William Hovis , Jack Mandelman , William Tonti
发明人： Roger Booth , William Hovis , Jack Mandelman , William Tonti
IPC分类号： H01L29/41
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An E-fuse and a method for fabricating an E-fuse integrating polysilicon resistor masks, and a design structure on which the subject E-fuse circuit resides are provided. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.
摘要翻译：一种电熔丝和一种用于制造集成多晶硅电阻掩模的电子熔丝的方法，以及设置有被检体E熔丝回路的设计结构。电熔丝包括限定熔丝形状的多晶硅层，其包括阴极，阳极和连接在阴极和阳极硅化物层之间的保险丝颈。硅化物形成在多晶硅层上形成，其中非硅化部分在靠近熔丝颈部的阴极的一部分上延伸。非接触部分基本上防止电流在阴极的硅化物形成区域中流动，在保险丝编程期间在保险丝颈部发生电迁移。非接触部分具有比熔丝颈部的串联电阻显着更低的串联电阻。

15. 发明申请

US20070241768A1 CHANGING CHIP FUNCTION BASED ON FUSE STATES 有权
标题翻译：基于保险丝状态改变芯片功能
公开(公告)号：US20070241768A1
公开(公告)日：2007-10-18
申请号：US11760575
申请日：2007-06-08
申请人： KARL ERICKSON , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： KARL ERICKSON , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： G11C8/20
CPC分类号： G06F21/71
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。操作和/或访问可以基于存储在诸如电可编程熔丝（eFUSES）的非易失性存储元件中的值来提供。

16. 发明申请

US20070210411A1 Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof 失效
标题翻译：具有位于不同高度的端子部分的电可编程熔丝结构及其制造方法
公开(公告)号：US20070210411A1
公开(公告)日：2007-09-13
申请号：US11372334
申请日：2006-03-09
申请人： William Hovis , Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： William Hovis , Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L21/82 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.
摘要翻译：提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处，并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。第一端子部分和第二端子部分平行于支撑表面定向，而熔丝元件包括垂直于支撑表面定向的部分，并且包括至少一个直角弯曲部，其从第一和第二端子部分中的至少一个过渡到保险丝元件的正交取向部分。

17. 发明申请

US20070205485A1 Programmable anti-fuse structures, methods for fabricating programmable anti-fuse structures, and methods of programming anti-fuse structures 审中-公开
标题翻译：可编程反熔丝结构，制造可编程反熔丝结构的方法以及编程反熔丝结构的方法
公开(公告)号：US20070205485A1
公开(公告)日：2007-09-06
申请号：US11366879
申请日：2006-03-02
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L29/00
CPC分类号： H01L27/1203 , H01L21/84 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： Programmable anti-fuse structures for semiconductor device constructions, fabrication methods for forming anti-fuse structures during semiconductor device fabrication, and programming methods for anti-fuse structures. The programmable anti-fuse structure comprises first and second terminals and an anti-fuse layer electrically coupled with the first and second terminals. An electrically-conductive diffusion layer is disposed between the first terminal and the anti-fuse layer. The diffusion layer inhibits diffusion of conductive material from the first terminal to the anti-fuse layer when the anti-fuse structure is unprogrammed, but permits diffusion of the conductive material when a programming voltage is applied between the first and second terminals during operation. Advantageously, the first terminal may be composed of metal and the anti-fuse layer may be composed of a semiconductor. The methods of fabricating the anti-fuse structure do not require an additional lithographic mask but instead rely on damascene process steps used to fabricate interconnection structures for neighboring active devices.
摘要翻译：用于半导体器件结构的可编程抗熔丝结构，在半导体器件制造期间形成抗熔丝结构的制造方法以及用于抗熔丝结构的编程方法。可编程反熔丝结构包括第一和第二端子以及与第一和第二端子电耦合的抗熔丝层。导电扩散层设置在第一端子和反熔丝层之间。当反熔丝结构未编程时，扩散层抑制导电材料从第一端子到抗熔丝层的扩散，但是当在操作期间在第一和第二端子之间施加编程电压时允许导电材料的扩散。有利地，第一端子可以由金属构成，并且抗熔丝层可以由半导体构成。制造抗熔丝结构的方法不需要额外的光刻掩模，而是依赖用于制造相邻有源器件的互连结构的镶嵌工艺步骤。

18. 发明申请

US20070190740A1 ENHANCED SILICON-ON-INSULATOR (SOI) TRANSISTORS AND METHODS OF MAKING ENHANCED SOI TRANSISTORS 审中-公开
标题翻译：增强型硅绝缘体（SOI）晶体管及其制造增强型SOI晶体管的方法
公开(公告)号：US20070190740A1
公开(公告)日：2007-08-16
申请号：US11733249
申请日：2007-04-10
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L21/76
CPC分类号： H01L29/78687 , H01L21/26533 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/66772 , H01L29/7842 , H01L29/7848 , H01L29/78603
摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.
摘要翻译：提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。

19. 发明申请

US20070189076A1 Memory elements and methods of using the same 失效
标题翻译：内存元素和使用方法
公开(公告)号：US20070189076A1
公开(公告)日：2007-08-16
申请号：US11353493
申请日：2006-02-14
申请人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
发明人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
IPC分类号： G11C16/04
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

20. 发明申请

US20070158779A1 Methods and semiconductor structures for latch-up suppression using a buried damage layer 审中-公开
标题翻译：使用掩埋损伤层进行闩锁抑制的方法和半导体结构
公开(公告)号：US20070158779A1
公开(公告)日：2007-07-12
申请号：US11330688
申请日：2006-01-12
申请人： Ethan Cannon , Toshiharu Furukawa , Robert Gauthier , David Horak , Jack Mandelman , William Tonti
发明人： Ethan Cannon , Toshiharu Furukawa , Robert Gauthier , David Horak , Jack Mandelman , William Tonti
IPC分类号： H01L29/00
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/823892 , H01L27/0921
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a damage layer formed in a substrate, a first doped well formed in the substrate, and a second doped well formed in the substrate proximate to the first doped well. The damage layer extends within the substrate to intersect the first and second doped wells. The damage layer may be formed by ion implantation followed by growth of an epitaxial layer to segregate the active device regions from the damage layer.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。该结构包括形成在衬底中的损伤层，在衬底中形成的第一掺杂阱，以及在靠近第一掺杂阱的衬底中形成的第二掺杂阱。损伤层在衬底内延伸以与第一和第二掺杂阱相交。可以通过离子注入形成损伤层，随后生长外延层以使有源器件区域与损伤层分离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式