会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 12. 发明申请
    • SPIROCHROMANON DERIVATIVES
    • 螺吡喃衍生物
    • US20090270436A1
    • 2009-10-29
    • US12518466
    • 2008-01-08
    • Tomoharu IinoHideki JonaHideki KuriharaMasayuki NakamuraKenji NiiyamaJun ShibataTadashi ShimamuraHitomi WatanabeTakeru YamakawaLihu Yang
    • Tomoharu IinoHideki JonaHideki KuriharaMasayuki NakamuraKenji NiiyamaJun ShibataTadashi ShimamuraHitomi WatanabeTakeru YamakawaLihu Yang
    • A61K31/438C07D401/14A61P3/00A61P35/00A61P31/00
    • C07D491/107C07D491/20C07D519/00
    • The invention relates to a compound of a general formula (I): wherein Ar1 represents a group formed from an aromatic ring selected from a group consisting of benzene, pyrazole, isoxazole, pyridine, indole, 1H-indazole, 1H-furo[2,3-c]pyrazole, 1H-thieno[2,3-c]pyrazole, benzimidazole, 1,2-benzisoxazole, imidazo[1,2-a]pyridine, imidazo[1,5-a]pyridine and 1H-pyrazolo[3,4-b]pyridine, having Ar2, and optionally having one or two or more substituents selected from R3: R1 and R2 each independently represent a hydrogen atom, a halogen atom, a cyano group, a C2-C6 alkenyl group, a C1-C6 alkoxy group, a C2-C7 alkanoyl group, a C2-C7 alkoxycarbonyl group, an aralkyloxycarbonyl group, a carbamoyl-C1-C6 alkoxy group, a carboxy-C2-C6 alkenyl group, or a group of -Q1-N(Ra)-Q2-Rb; or a C1-C6 alkyl group optionally having a substituent; or an aryl or heterocyclic group optionally having a substituent; or a C1-C6 alkyl group or a C2-C6 alkenyl group having the aryl or heterocyclic group; T and U each independently represent a nitrogen atom or a machine group; and V represents an oxygen atom or a sulfur atom. The compound of the invention is useful as therapeutical agents for various ACC-related diseases.
    • 本发明涉及通式(I)的化合物:其中Ar 1表示由选自苯,吡唑,异恶唑,吡啶,吲哚,1H-吲唑,1H-呋喃并[ 3-c]吡唑,1H-噻吩并[2,3-c]吡唑,苯并咪唑,1,2-苯并异恶唑,咪唑并[1,2-a]吡啶,咪唑并[1,5-a]吡啶和1H-吡唑并[ 具有Ar 2且任选具有一个或两个以上选自R 3:R 1和R 2的取代基的3,4-b]吡啶各自独立地表示氢原子,卤素原子,氰基,C 2 -C 6烯基, C1-C6烷氧基,C2-C7烷酰基,C2-C7烷氧基羰基,芳烷氧基羰基,氨基甲酰基C1-C6烷氧基,羧基-C2-C6链烯基或-Q1-N (Ra)-Q2-Rb; 或任选具有取代基的C1-C6烷基; 或任选具有取代基的芳基或杂环基; 或具有芳基或杂环基的C 1 -C 6烷基或C 2 -C 6烯基; T和U各自独立地表示氮原子或机组; V表示氧原子或硫原子。 本发明的化合物可用作各种ACC相关疾病的治疗剂。
    • 15. 发明授权
    • EEPROM cell having reduced cell area
    • EEPROM单元具有减小的单元面积
    • US06573557B1
    • 2003-06-03
    • US09552441
    • 2000-04-18
    • Hitomi Watanabe
    • Hitomi Watanabe
    • H01L29788
    • H01L27/11521H01L27/115H01L27/11558H01L29/42324H01L29/7883
    • An EEPROM cell having one layer of polycrystalline silicon in which a memory cell area is reduced without damaging cell characteristics by providing a channel length of a select gate transistor and a channel length of a cell transistor to extend perpendicularly to each other, and that a select gate electrode and a control gate electrode of an impurity diffusion layer are arranged in parallel with each other, and a cell source wiring is made of a metal wiring through a contact, so that a parasitic transistor on the control gate wiring is eliminated and it becomes possible to effectively reduce the cell area.
    • 具有一层多晶硅的EEPROM单元,其中通过提供选择栅晶体管的沟道长度和单元晶体管的沟道长度彼此垂直地延伸而使存储单元面积减小而不损坏单元特性,并且选择 栅极电极和杂质扩散层的控制栅极电极彼此并联布置,并且电池源布线通过接触由金属布线构成,从而消除了控制栅极布线上的寄生晶体管,并且其变为 可能有效地减少细胞面积。
    • 16. 发明授权
    • Method of producing semiconductor having two-layer polycrystalline silicon structure
    • 制造具有两层多晶硅结构的半导体的方法
    • US06420222B1
    • 2002-07-16
    • US09047859
    • 1998-03-25
    • Hitomi Watanabe
    • Hitomi Watanabe
    • H01L218238
    • H01L27/11526H01L27/0629H01L27/105H01L27/11529H01L28/60
    • In a semiconductor manufacturing process for a semiconductor device having two layers of polycrystalline silicon and a Double Diffused Drain (DDD) type transistor, the number of heat treatment processes is minimized to avoid degrading the quality of a gate oxide film, such as a tunnel oxide film in an EEPROM. After forming a gate electrode of a DDD transistor and a lower electrode of a capacitor, for example, of a first polycrystalline silicon film, a DDD impurity diffusion region is formed by a heat treatment process combined with a thermal oxide growth process for producing an oxide dielectric for the capacitor and a gate oxide of a peripheral transistor. A second polycrystalline silicon film is then formed as a gate electrode of the peripheral transistor and an upper electrode of the capacitor, thereby reducing the number of process steps and improving the quality of the gate oxide film and a tunnel oxide film by reducing the length of the heat treatment processes.
    • 在具有两层多晶硅和双扩散漏极(DDD)型晶体管的半导体器件的半导体制造工艺中,热处理工艺的数量被最小化以避免降低诸如隧道氧化物的栅极氧化膜的质量 电影在EEPROM中。 在形成DDD晶体管的栅电极和例如第一多晶硅膜的电容器的下电极之后,通过与用于制备氧化物的热氧化物生长工艺结合的热处理工艺形成DDD杂质扩散区域 用于电容器的电介质和外围晶体管的栅极氧化物。 然后形成第二多晶硅膜作为外围晶体管的栅电极和电容器的上电极,从而减少工艺步骤的数量,并且通过减小栅极氧化膜和隧道氧化物膜的长度来降低栅极氧化膜的质量 热处理工艺。
    • 17. 发明授权
    • Semiconductor device having defects of deep level generated by electron
beam irradiation in a semiconductor substrate
    • 半导体衬底中具有由电子束照射产生的深度电平的缺陷的半导体器件
    • US5672906A
    • 1997-09-30
    • US588395
    • 1996-01-18
    • Yutaka SaitoTakao AkibaKoju NonakaMasaaki KamiyaHitomi Watanabe
    • Yutaka SaitoTakao AkibaKoju NonakaMasaaki KamiyaHitomi Watanabe
    • H01L27/092H01L29/32H01L29/30
    • H01L29/32H01L27/0921
    • The present invention is provided for improving latch-up resistance in a semiconductor integrated circuit device employing CMOS structure, for preventing the photoelectric carriers from getting into the sensors and improving the afterimage characteristic in a semiconductor image sensor device, and for impurity the switching characteristic in a semiconductor device having bipolar element. An electron beam of over 2 MeV and 1E15/cm.sup.2 is irradiated to a monocrystal silicon semiconductor region in a substrate and then annealing is performed at a high temperature of over 200.degree. C. As a result, at 150 K., a shallow level traps of which the activation energy from a valence band EV is under 0.1 eV and which is produced at the concentration of about 1.2-1.7E15/cm.sup.3, and a deep level traps of which the activation energy is 0.28-0.32 eV and which is produced at the concentration of about 1.6-2.0E13/cm.sup.3 are obtained. Then a semiconductor substrate having both the level traps stated above as recombination centers in a band gap of silicon is obtained. The chip size of this semiconductor substrate doesn't increase, and furthermore the cost of it is low as an epi wafer is not used. As well, it is possible to manufacture a semiconductor integrated circuit device just before or just after a process step of evaluating the electrical characteristic of a semiconductor integrated circuit device.
    • 本发明提供了用于提高采用CMOS结构的半导体集成电路器件中的闭锁电阻,用于防止光电载体进入传感器并提高半导体图像传感器装置中的残留图像特性, 具有双极性元件的半导体器件。 将超过2MeV和1E15 / cm2的电子束照射到衬底中的单晶硅半导体区域,然后在超过200℃的高温下进行退火。结果,在150K下,浅层陷阱 其中价带EV的活化能低于0.1eV,其浓度约为1.2-1.7E15 / cm3,其中活化能为0.28-0.32eV,深度浓度为 得到约1.6-2.0E13 / cm3的浓度。 然后,获得具有上述两级电平阱的半导体衬底作为硅的带隙中的复合中心。 该半导体衬底的芯片尺寸不增加,并且由于不使用epi晶片,因此其成本较低。 同样,可以在评估半导体集成电路器件的电特性的工艺步骤之前或之后制造半导体集成电路器件。
    • 20. 发明授权
    • Semiconductor integrated circuit device having MOS transistor
    • 具有MOS晶体管的半导体集成电路器件
    • US07161198B2
    • 2007-01-09
    • US10236413
    • 2002-09-06
    • Toshihiko OmiHitomi WatanabeKazutoshi IshiiNaoto Saitoh
    • Toshihiko OmiHitomi WatanabeKazutoshi IshiiNaoto Saitoh
    • H01L29/76
    • H01L29/7816H01L29/0878H01L29/1083H01L29/1095H01L29/42368H01L29/7833H01L29/7835
    • An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a parasitic NPN transistor formed among the drain, the well, and the semiconductor substrate which are arranged in the stated order. According to the present invention, provided are a semiconductor device, including: a semiconductor substrate; an epitaxial layer having an electric polarity identical with that of the semiconductor substrate, which is formed on the semiconductor substrate; a buried diffusion layer having the electric polarity different from that of the semiconductor substrate, which is formed between the semiconductor substrate and the epitaxial layer; and a well region having the electric polarity identical with that of the buried diffusion layer, which is formed above the buried diffusion layer and is electrically connected therewith, in which a MOS transistor is formed in a well having a structure in which the buried diffusion layer is electrically connected with the well region, and a manufacturing method therefor.
    • 具有高耐受电压的半导体器件的N沟道MOS晶体管采用具有低浓度和大扩散深度的漏极结构,这导致由于形成的寄生NPN晶体管而不能获得足够高的耐受电压的问题 在排列,阱和半导体衬底之中,以所述顺序排列。 根据本发明,提供一种半导体器件,包括:半导体衬底; 具有与半导体衬底的电极性相同的电极的外延层,其形成在半导体衬底上; 形成在半导体衬底和外延层之间的具有与半导体衬底的电极性不同的电极的掩埋扩散层; 以及具有与掩埋扩散层的电极性相同的电极性的阱区,其形成在掩埋扩散层的上方并与其电连接,其中MOS晶体管形成在具有埋入扩散层的结构的阱中, 与该阱区电连接,及其制造方法。