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11. 发明授权

US06790722B1 Logic SOI structure, process and application for vertical bipolar transistor 有权
标题翻译：逻辑SOI结构，工艺和应用于垂直双极晶体管
公开(公告)号：US06790722B1
公开(公告)日：2004-09-14
申请号：US09718850
申请日：2000-11-22
申请人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer , William R. Tonti
发明人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer , William R. Tonti
IPC分类号： H01L218238
CPC分类号： H01L29/66265 , H01L21/8249 , H01L27/0623 , H01L29/7317
摘要： A method and structure for forming an emitter in a vertical bipolar transistor includes providing a substrate having a collector layer and a base layer over the collector layer, forming a patterning mask over the collector layer, and filling openings in the mask with emitter material in a damascene process. The CMOS/vertical bipolar structure has the collector, base regions, and emitter regions vertically disposed on one another, the collector region having a peak dopant concentration adjacent the inter-substrate isolation oxide.
摘要翻译：用于在垂直双极晶体管中形成发射极的方法和结构包括在集电极层上提供具有集电极层和基极层的衬底，在集电极层上形成图案掩模，并在发光体材料中填充掩模中的开口大马士革过程。 CMOS /垂直双极结构具有彼此垂直设置的集电极，基极区域和发射极区域，集电极区域具有与衬底间隔离氧化物相邻的峰值掺杂剂浓度。

12. 发明授权

US06658634B1 Logic power optimization algorithm 失效
标题翻译：逻辑功率优化算法
公开(公告)号：US06658634B1
公开(公告)日：2003-12-02
申请号：US09073999
申请日：1998-05-07
申请人： Kenneth J. Goodnow , Michel S. Michail , Clarence R. Ogilvie , Wilbur D. Pricer , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Michel S. Michail , Clarence R. Ogilvie , Wilbur D. Pricer , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5022 , G06F2217/78
摘要： Disclosed is a system and method for eliminating the unnecessary toggling of logic in a logic network. The method and system can be incorporated directly into logic synthesis software, or may be implemented manually. Provided is a mechanism for identifying critical nets and then inserting net latches at the critical nets wherein each net latch is controlled by an enable signal that also controls a related output latch. Each net latch is comprised of a circuit which can on command hold static the last logic level on a given logic node.
摘要翻译：公开了一种用于消除在逻辑网络中不必要的逻辑切换的系统和方法。该方法和系统可以直接并入逻辑综合软件中，或者可以手动实现。提供了用于识别关键网络，然后在关键网络处插入网络锁存器的机制，其中每个网络锁存器由也控制相关输出锁存器的使能信号控制。每个网络锁存器包括一个电路，该电路可以在命令上保持给定逻辑节点上的最后一个逻辑电平。

13. 发明授权

US06344679B1 Diode with alterable conductivity and method of making same 失效
标题翻译：具有可变导电性的二极管及其制造方法
公开(公告)号：US06344679B1
公开(公告)日：2002-02-05
申请号：US09443524
申请日：1999-11-19
申请人： William A. Klaasen , Wilbur D. Pricer , Jed Hickory Rankin
发明人： William A. Klaasen , Wilbur D. Pricer , Jed Hickory Rankin
IPC分类号： G11C1706
CPC分类号： H01L23/5258 , G11C17/06 , G11C17/16 , H01L23/5254 , H01L27/0814 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (102) having a plurality of diodes (100) with alterable electrical conductivity by a source of energy (30), e.g., a laser, external to the semiconductor device. The diodes are formed and energy is applied to alter the electrical conductivity at least 10%, and preferably by several orders of magnitude. Certain embodiments (20, 40 and 50) are formed so as to function as anti-fuses, while another embodiment (60) functions as a fuse. The diodes may be formed as planar diodes (20, 40, 50 and 60) or as lateral diodes (70).
摘要翻译：一种具有多个二极管（100）的半导体器件（102），所述多个二极管（100）具有通过所述半导体器件外部的能量源（30）例如激光器具有可改变的导电性。形成二极管并施加能量以改变至少10％的电导率，优选地几个数量级。某些实施例（20,40和50）被形成为用作抗熔丝，而另一个实施例（60）用作保险丝。二极管可以形成为平面二极管（20,40,50和60）或形成为侧向二极管（70）。

14. 发明授权

US6020777A Electrically programmable anti-fuse circuit 失效
标题翻译：电子可编程反熔丝电路
公开(公告)号：US6020777A
公开(公告)日：2000-02-01
申请号：US938754
申请日：1997-09-26
申请人： John A. Bracchitta , Wilbur D. Pricer
发明人： John A. Bracchitta , Wilbur D. Pricer
IPC分类号： G11C17/16 , H01H37/76
CPC分类号： G11C17/16
摘要： An array of anti-fuse cells forming rows and columns of a matrix is described. The anti-fuse cell includes an MOS capacitor connected to a source of high voltage which is capable of rendering the capacitor permanently conductive. A first voltage limiting transistor connects the free end of the MOS capacitor to a second transistor. An address decoder provides address signals to a source and gate of the second transistor within the cell. The MOS capacitor is rendered permanently conductive when the first and second transistors are rendered conductive. The high voltage is confined to the MOS capacitor, which is fused through the high current being drawn through the capacitor by the first and second transistors. Other components on the integrated circuit carrying the array of fusible cells are maintained free of any high voltage.
摘要翻译：描述形成矩阵行和列的反熔丝单元的阵列。反熔丝单元包括连接到能够使电容器永久导电的高电压源的MOS电容器。第一电压限制晶体管将MOS电容器的自由端连接到第二晶体管。地址解码器向单元内的第二晶体管的源极和栅极提供地址信号。当第一和第二晶体管导通时，MOS电容器被永久导通。高电压被限制在MOS电容器中，MOS电容器通过第一和第二晶体管通过电容器吸收的高电流熔断。携带易熔电池阵列的集成电路上的其他部件保持不受任何高电压的影响。

15. 发明授权

US6011383A Low powering apparatus for automatic reduction of power in active and standby modes 失效
标题翻译：用于在主动和待机模式下自动降低功率的低功率设备
公开(公告)号：US6011383A
公开(公告)日：2000-01-04
申请号：US120211
申请日：1998-07-21
申请人： Alvar A. Dean , Kenneth J. Goodnow , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
发明人： Alvar A. Dean , Kenneth J. Goodnow , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1/32 , G05F1/110 , G06F1/00
CPC分类号： G06F1/3296 , G06F1/3203 , Y02B60/1285
摘要： A low powering apparatus for automatic reduction of power in active and standby modes is disclosed. The low powering apparatus includes a state detector, a margins of safety device and a positioning device. The state detector detects a first or second state, such as a standby state and an active state, that has predominated in a recent past. The margins of safety device indicates safe low power margins in correlation to the detected first or second state. The positioning device adjusts the power level according to the outputs of the state detector and margins of safety device. Thus, the low powering apparatus minimizes the power level of a system at the first or second state without compromising full performance of the system.
摘要翻译：公开了一种用于在主动和待机模式下自动降低功率的低功率设备。低功率装置包括状态检测器，安全装置的边缘和定位装置。状态检测器检测在最近过去占主导地位的第一或第二状态，例如待机状态和活动状态。安全装置的边缘表示与检测到的第一或第二状态相关的安全低功率余量。定位装置根据状态检测器的输出和安全装置的余量调整功率水平。因此，低功率设备使系统在第一或第二状态下的功率水平最小化，而不会影响系统的全部性能。

16. 发明授权

US5999037A Circuit for operating a control transistor from a fusible link 失效
标题翻译：用于从可熔链路操作控制晶体管的电路
公开(公告)号：US5999037A
公开(公告)日：1999-12-07
申请号：US904397
申请日：1997-07-31
申请人： Kerry Bernstein , Daniel C. Edelstein , William A. Klaasen , Wilbur D. Pricer
发明人： Kerry Bernstein , Daniel C. Edelstein , William A. Klaasen , Wilbur D. Pricer
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/785
摘要： A circuit for enabling a controlled transistor in response to an ablated fusible link. The fusible link is configured so that no d.c. potential resides on the link once it has been ablated. A source of alternating voltage is capacitively coupled to the fusible link and maintains the fusible link from reconnection due to dendrite formation once it is ablated. An a.c. to d.c. voltage converter is used to signal the change in condition of the fusible link, thus, actuating a control transistor of a redundant circuit element in a replacement operation.
摘要翻译：一种用于响应于消融的可熔链路启用受控晶体管的电路。熔丝链接被配置为没有直流一旦消融，电位就位于链接上。交流电压源电容耦合到可熔链路，并且一旦烧蚀就会由于枝晶形成而使可熔连接件重新连接。一个到达电压转换器用于发信号通知熔断条件的变化，从而在更换操作中致动冗余电路元件的控制晶体管。

17. 发明授权

US5873053A On-chip thermometry for control of chip operating temperature 失效
标题翻译：用于芯片工作温度的片上测温
公开(公告)号：US5873053A
公开(公告)日：1999-02-16
申请号：US841967
申请日：1997-04-08
申请人： Wilbur D. Pricer , Wendell P. Noble , John A. Fifield , John E. Gersbach
发明人： Wilbur D. Pricer , Wendell P. Noble , John A. Fifield , John E. Gersbach
IPC分类号： G01K7/01
CPC分类号： G01K7/01 , Y10S323/907
摘要： Temperatures on a chip, including particular regions of a chip are monitored by sensing changes in sub-threshold conduction of a field effect transistor (FET) integrated on the chip due to changes in charge carrier population distribution with temperature therein. Such changes in sub-threshold current with temperature are preferably detected using a current mirror and two FETs with different channel geometry and slightly different gate voltages such that the currents are equal at a specific design temperature. The slightly different gate voltages are conveniently provided by a low current voltage divider with or without on-chip voltage regulation in which resistor ratios can be accurately and repeatably obtained. Variations from that temperature thus yield large current differences and substantial signal swing which improve noise immunity. Hysteresis can be applied to the output (or amplified output) of the current mirror to obtain bistable thermostat-like action. Variant applications provide sensing at plural chip locations (e.g. for sensing temperature gradients and temperatures of autonomously operating portions of the chip) and a plurality of temperatures on the chip. Temperatures thus monitored control implementation of performance enhancing algorithms in regard to the chip.
摘要翻译：通过感测集成在芯片上的场效应晶体管（FET）的亚阈值传导的变化，由于载流子群体分布随温度的变化而监测芯片上包括芯片的特定区域的温度。亚阈值电流随温度的这种变化优选使用电流镜和具有不同通道几何形状和略微不同的栅极电压的两个FET来检测，使得电流在特定设计温度下是相等的。通过具有或不具有片内电压调节的低电流分压器可以方便地提供略微不同的栅极电压，其中可以精确和重复地获得电阻器比率。因此，该温度的变化产生大的电流差异和显着的信号摆动，这提高了抗噪声性。迟滞可应用于电流镜的输出（或放大输出），以获得双稳态恒温器状作用。变体应用提供在多个芯片位置处的感测（例如用于感测芯片的自主操作部分的温度梯度和温度）以及芯片上的多个温度。因此监控的温度控制了关于芯片的性能增强算法的实现。

18. 发明授权

US4675559A Differential circuit having a high voltage switch 失效
标题翻译：差分电路具有高压开关
公开(公告)号：US4675559A
公开(公告)日：1987-06-23
申请号：US628878
申请日：1984-07-09
申请人： Peter E. Cottrell , John E. Gersbach , Wilbur D. Pricer
发明人： Peter E. Cottrell , John E. Gersbach , Wilbur D. Pricer
IPC分类号： H03K5/02 , H03K17/16 , H03K19/003
CPC分类号： H03K5/02
摘要： This invention provides a differential circuit having first and second transistors interconnected by a third transistor which is symmetrically constructed. A current source is selectively connected to the base of the third transistor. When the current source is connected to the base of the third transistor, the third transistor is saturated, forming a very low impedance path between the first and second transistors. However, when the current source is disconnected from the base of the third transistor, the third transistor impedes the voltage breakdown path between the bases of the first and second transistors. The differential circuit is particularly useful in an improved compact magnetic media system wherein both the stored signal and the write signal or voltage are applied to the bases of the first and second transistor of the circuit without the high write voltages destroying the high performance first and second transistors.
摘要翻译：本发明提供一种差分电路，其具有通过对称构造的第三晶体管互连的第一和第二晶体管。电流源选择性地连接到第三晶体管的基极。当电流源连接到第三晶体管的基极时，第三晶体管饱和，在第一和第二晶体管之间形成非常低的阻抗路径。然而，当电流源与第三晶体管的基极断开时，第三晶体管阻止第一和第二晶体管的基极之间的电压击穿路径。差分电路在改进的小型磁介质系统中特别有用，其中存储的信号和写入信号或电压都被施加到电路的第一和第二晶体管的基极，而没有高写入电压破坏高性能的第一和第二晶体管。

19. 发明授权

US4384216A Controlled power performance driver circuit 失效
标题翻译：受控电源性能驱动电路
公开(公告)号：US4384216A
公开(公告)日：1983-05-17
申请号：US180242
申请日：1980-08-22
申请人： Wilbur D. Pricer
发明人： Wilbur D. Pricer
IPC分类号： H03K5/02 , H03K17/687 , H03K19/0944 , H03K5/12
CPC分类号： H03K5/023 , H03K19/09445
摘要： The circuit rapidly charges and discharges a load capacitor by sensing the direction of transients at an internal node of the circuit which is selectively isolated from a capacitive output node to produce significant load current during upward transients. In an embodiment of the invention, the circuit includes a driver device and first, second and third field effect transistors. The first transistor is connected between a voltage supply terminal and the driver device forming an internal node between the first transistor and the driver device and acts as a current source pulling up the internal node. The second transistor is connected between the internal node and an output node and is arranged to selectively isolate the internal node from the output node, with isolation increasing during a positive transient to allow maximum drive to the third transistor connected between the voltage supply terminal and the output node to produce increased output current. The second transistor is also arranged to minimize the isolation between the internal and output nodes during negative transients to rapidly discharge the output node.
摘要翻译：该电路通过感测电路的内部节点的瞬态方向快速充电和放电负载电容器，该方式与电容输出节点选择性隔离，从而在向上瞬变期间产生显着的负载电流。在本发明的一个实施例中，电路包括驱动器器件和第一，第二和第三场效应晶体管。第一晶体管连接在电压源端子和驱动器器件之间，该驱动器器件在第一晶体管和驱动器器件之间形成内部节点，并用作提升内部节点的电流源。第二晶体管连接在内部节点和输出节点之间，并且被布置为选择性地将内部节点与输出节点隔离，在正瞬变期间隔离增加，以允许对连接在电压供应端和第输出节点产生增加的输出电流。第二晶体管还被布置为在负瞬态期间最小化内部和输出节点之间的隔离以快速放电输出节点。

20. 发明授权

US4216573A Three mask process for making field effect transistors 失效
标题翻译：制作场效应晶体管的三个掩模工艺
公开(公告)号：US4216573A
公开(公告)日：1980-08-12
申请号：US904182
申请日：1978-05-08
申请人： Madhukar L. Joshi , Richard K. Mason , Wilbur D. Pricer
发明人： Madhukar L. Joshi , Richard K. Mason , Wilbur D. Pricer
IPC分类号： H01L21/336 , H01L29/417 , H01L29/78 , B01J17/00
CPC分类号： H01L29/78
摘要： A three mask method is provided for making a field effect transistor which includes the use of a first mask for defining first and second spaced apart diffusion regions, each having first and second ends, a second mask for defining a contact region at the first end of the first and second diffusion regions and for defining a protected region at the gate region and source and drain electrodes of the transistor, the protected region extending between the second ends of the first and second diffusion regions, and a third mask for forming a gate electrode within the protected region and contact electrodes in the contact region. The source and drain electrodes are formed between the gate electrode and the first and second diffusion regions by ion implantation techniques. The surfaces of the first and second diffusion regions between the contact electrodes and the second end of the first and second diffusions are oxidized to provide a crossover arrangement for gate electrode wiring, when desired, without requiring additional process steps.
摘要翻译：提供三掩模方法用于制造场效应晶体管，其包括使用第一掩模来限定第一和第二间隔开的扩散区域，每个第一和第二间隔扩散区域具有第一和第二端，第二掩模，用于限定第一和第二端部处的接触区域所述第一和第二扩散区域以及用于在所述晶体管的栅极区域和源极和漏极电极处限定保护区域，所述保护区域在所述第一和第二扩散区域的第二端之间延伸，以及用于形成栅电极的第三掩模在受保护区域内和接触区域中的接触电极。源极和漏极通过离子注入技术形成在栅电极和第一和第二扩散区之间。在需要的情况下，在接触电极和第一和第二扩散的第二端之间的第一和第二扩散区域的表面被氧化以提供用于栅极电极布线的交叉布置，而不需要额外的工艺步骤。

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