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1. 发明授权

US06880074B2 In-line code suppression 失效
标题翻译：在线代码抑制
公开(公告)号：US06880074B2
公开(公告)日：2005-04-12
申请号：US09681077
申请日：2000-12-22
申请人： Patrick E. Perry , Sebastian T. Ventrone
发明人： Patrick E. Perry , Sebastian T. Ventrone
IPC分类号： G06F1/32 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/45 , G06F9/54 , G06F9/445
CPC分类号： G06F9/30069 , G06F1/3203 , G06F1/329 , G06F8/4432 , G06F9/30145 , Y02D10/24 , Y02D10/41
摘要： Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes) singly or in groups in accordance with one or more execution bits set during post-processing in opcodes preceding opcodes to be skipped. Thus portions of an application program which consume excessive power or are unsupported in particular operating environments can be easily and selectively de-activate while maintaining the integrity of the applications program. Local or cache memory is also effectively expanded and processor performance improved by eliminating opcodes from local or cache memory which will not be called.
摘要翻译：通过根据在后处理期间设置的一个或多个执行位单独或分组跳过操作代码（操作码），处理器开销降低，特别是处理速度和功率节省，提高处理器性能，允许实时处理器重新启动操作码之前的操作码将被跳过。因此，在保持应用程序的完整性的同时，可以容易地和选择性地去激活在特定操作环境中消耗过多功率或不受支持的应用程序的部分。还可以通过从本地或高速缓冲存储器中消除不被调用的操作码来有效地扩展本地或高速缓冲存储器并提高处理器性能。

2. 发明授权

US06802033B1 Low-power critical error rate communications controller 失效
标题翻译：低功率关键错误率通信控制器
公开(公告)号：US06802033B1
公开(公告)日：2004-10-05
申请号：US09286855
申请日：1999-04-06
申请人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1100
CPC分类号： G06F11/10 , H04L1/0053
摘要： A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.
摘要翻译：一种在通信控制器上动态修改错误恢复的方式，以在当前错误率条件允许的最低功耗模式下工作。当操作条件良好并且检测到少量错误时，输入低功率错误检测/校正模式，从而节省电池寿命。低功率误差校正机构运行频率较低，功率低于大功率机构，并为控制器保持相同的数据速率，从而节省功耗。选择控制器错误（电源）模式可以是外部的，例如当语音数据太嘈杂时，人们在蜂窝电话上使用控制拨盘。或者，选择可以是自动的，在内部进行选择的关键误差电平检测器。

3. 发明授权

US06678847B1 Real time function view system and method 失效
标题翻译：实时功能查看系统和方法
公开(公告)号：US06678847B1
公开(公告)日：2004-01-13
申请号：US09303211
申请日：1999-04-30
申请人： Patrick E. Perry , Sebastian T. Ventrone
发明人： Patrick E. Perry , Sebastian T. Ventrone
IPC分类号： G01R3128
CPC分类号： G01R31/318555 , G01R31/318538 , G06F9/30116 , G06F11/3648
摘要： A system and method for determining the operational state of a logic device having a plurality of shadow registers, each associated with one of a plurality of functional registers. Data stored in a functional register is, under selected conditions, also stored in an associated shadow register. These conditions include without limitation receipt by the functional register of predetermined event information such as an opcode, memory address or other information. Data in a given set of functional registers, e.g., registers making up pipeline stages in a microprocessor, may be stored in shadow registers simultaneously or sequentially when given data reaches a given register in the set. Additionally, data is stored in the shadow registers without interrupting execution cycles of the logic device.
摘要翻译：一种用于确定具有多个影子寄存器的逻辑设备的操作状态的系统和方法，每个影子寄存器与多个功能寄存器之一相关联。存储在功能寄存器中的数据在选定的条件下也存储在相关的影子寄存器中。这些条件包括但不限于功能寄存器对诸如操作码，存储器地址或其他信息的预定事件信息的接收。当给定数据到达集合中的给定寄存器时，给定的一组功能寄存器（例如，组成微处理器中的流水线级的寄存器）中的数据可以同时或顺序存储在影子寄存器中。此外，数据存储在影子寄存器中，而不会中断逻辑器件的执行周期。

4. 发明授权

US5784575A Output driver that parks output before going tristate 失效
标题翻译：输出驱动器，在三态之前停放输出
公开(公告)号：US5784575A
公开(公告)日：1998-07-21
申请号：US685128
申请日：1996-07-24
申请人： Steven F. Oakland , Bijit T. Patel , Patrick E. Perry
发明人： Steven F. Oakland , Bijit T. Patel , Patrick E. Perry
IPC分类号： G06F13/40 , H03K19/094 , G06F13/00
CPC分类号： G06F13/4072 , H03K19/09429
摘要： Disclosed is a tristate circuit driver capable of both parking the output in a deasserted state and switching to a tristate mode in less than one clock cycle. In a preferred embodiment, the driver circuitry utilized a delay device to generate a pulse signal immediately after the transition in an enable signal is detected. The pulse signal then causes the tristate driver to output a signal of a predetermined voltage for a duration of less then one clock cycle.
摘要翻译：公开了一种三态电路驱动器，其能够将输出停止在无效状态并且在不到一个时钟周期内切换到三态模式。在优选实施例中，驱动器电路利用延迟器件在检测到使能信号中的转变之后立即产生脉冲信号。然后脉冲信号使三态驱动器在小于一个时钟周期的持续时间内输出预定电压的信号。

5. 发明授权

US06317840B1 Control of multiple equivalent functional units for power reduction 有权
标题翻译：控制功率降低的多个等效功能单元
公开(公告)号：US06317840B1
公开(公告)日：2001-11-13
申请号：US09275170
申请日：1999-03-24
申请人： Alvar A. Dean , Kenneth J. Goodnow , Patrick E. Perry , Sebastian T. Ventrone
发明人： Alvar A. Dean , Kenneth J. Goodnow , Patrick E. Perry , Sebastian T. Ventrone
IPC分类号： G06F132
CPC分类号： G06F9/3885 , G06F1/3203 , G06F1/3287 , G06F1/3293 , G06F9/3836 , G06F9/3869 , Y02D10/122 , Y02D10/171
摘要： A processor with multiple equivalent functional units for power reduction, which includes a mechanism for controlling the selection of functional units. Specifically, the processor comprises a first circuit performing a predetermined function at a first speed, a second circuit for performing the same predetermined function at a second speed, and a control system for selecting either the first or second circuit to perform the function. The control system further includes a mechanism for controlling the rate of execution of the processor instructions in the pipeline in order to compensate for the speed at which the first or second circuit was performing the predetermined function.
摘要翻译：具有用于功率降低的多个等效功能单元的处理器，其包括用于控制功能单元的选择的机构。具体地，处理器包括以第一速度执行预定功能的第一电路，以第二速度执行相同的预定功能的第二电路，以及用于选择第一或第二电路以执行功能的控制系统。控制系统还包括用于控制流水线中的处理器指令的执行速率以便补偿第一或第二回路执行预定功能的速度的机构。

6. 发明申请

US20080215237A1 DESIGN STRUCTURE FOR ADAPTIVE ROUTE PLANNING FOR GPS-BASED NAVIGATION 审中-公开
标题翻译：基于GPS的导航自适应路由规划的设计结构
公开(公告)号：US20080215237A1
公开(公告)日：2008-09-04
申请号：US12054685
申请日：2008-03-25
申请人： Patrick E. Perry
发明人： Patrick E. Perry
IPC分类号： G01C21/34 , G01S5/00
CPC分类号： G01C21/3484
摘要： Disclosed herein is a design structure for route planning for global positioning system (GPS) based navigation systems. The method identifies route segments used in a GPS based navigation system and records an actual historical time of travel for at least one route segment traveled by users of the GPS based navigation system travel. The actual historical time of travel comprises the amount of time taken by a user of the GPS based navigation system to go from a beginning of the route segment to an end of the route segment. With embodiments herein, the day and time that the route segment was recorded is also noted. Then, the actual historical time of travel and the day and time for the route segment can be stored in a database. This information can be stored for a single-user or can be combined from a plurality users of the GPS based navigation systems.
摘要翻译：这里公开了用于基于全球定位系统（GPS）的导航系统的路线规划的设计结构。该方法识别在基于GPS的导航系统中使用的路线段，并且记录由基于GPS的导航系统旅行的用户行进的至少一个路线段的实际历史旅行时间。实际的旅行历史时间包括基于GPS的导航系统的用户从路线段的开始到路线段的结束所花费的时间量。对于本文的实施例，还记录了路线段被记录的日期和时间。然后，旅行的实际历史时间和路线段的日期和时间可以存储在数据库中。该信息可以存储为单个用户，或可以从基于GPS的导航系统的多个用户组合。

7. 发明授权

US06269468B1 Split I/O circuit for performance optimization of digital circuits 失效
标题翻译：分离式I / O电路，用于数字电路的性能优化
公开(公告)号：US06269468B1
公开(公告)日：2001-07-31
申请号：US09260453
申请日：1999-03-02
申请人： Alvar Dean , Patrick E. Perry , Sebastian Ventrone
发明人： Alvar Dean , Patrick E. Perry , Sebastian Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/78
摘要： A logic circuit device and circuit design methodology includes a “split-book” logic circuit design having different active device sizes with outputs for connections to both critical and non-critical digital circuit paths. By using “split” book designs with separate input and output stages, better silicon utilization, power optimization, and performance results. This is because each split book is designed with multiple output buffers that may be configured to optimally drive critical and non-critical paths. During the power/performance optimization phase of the design, timing critical paths of the design are first identified, with each path being optimized on its own basis. First the input stage of the strand may be improved with a stronger drive on the input port of the book. Only the input port that has been linked to a critical path is updated. The other input pins are left at their default setting. Then, the output buffers may then be connected together according to criticality of the path and net capacitive load they are driving. Different split book input/output circuit combinations may be attempted during the design phase until an optimal tradeoff between power optimization and performance is reached.
摘要翻译：逻辑电路器件和电路设计方法包括具有不同有源器件尺寸的“分离式”逻辑电路设计，其输出用于连接关键和非关键数字电路路径。通过使用具有独立输入和输出级的“拆分”书籍设计，更好的硅利用率，功耗优化和性能结果。这是因为每个拆分书都设计有多个输出缓冲区，可以配置为最佳地驱动关键路径和非关键路径。在设计的功率/性能优化阶段期间，首先确定设计的时序关键路径，每个路径都以其自身为基础进行优化。首先，可以通过在书的输入端口上的更强的驱动来改进链的输入阶段。仅链接到关键路径的输入端口已更新。其他输入引脚保持默认设置。然后，输出缓冲器然后可以根据它们正在驱动的路径和净电容负载的关键性被连接在一起。可以在设计阶段尝试不同的分页输入/输出电路组合，直到达到功率优化和性能之间的最佳权衡。

8. 发明申请

US20070271034A1 ADAPTIVE ROUTE PLANNING FOR GPS-BASED NAVIGATION 审中-公开
标题翻译：用于GPS导航的自适应路由规划
公开(公告)号：US20070271034A1
公开(公告)日：2007-11-22
申请号：US11383786
申请日：2006-05-17
申请人： Patrick E. Perry
发明人： Patrick E. Perry
IPC分类号： G01C21/34
CPC分类号： G01C21/3492
摘要： Disclosed herein is a method of route planning for global positioning system (GPS) based navigation systems. The method identifies route segments used in a GPS based navigation system and records an actual historical time of travel for at least one route segment traveled by users of the GPS based navigation system travel. The actual historical time of travel comprises the amount of time taken by a user of the GPS based navigation system to go from a beginning of the route segment to an end of the route segment. With embodiments herein, the day and time that the route segment was recorded is also noted. Then, the actual historical time of travel and the day and time for the route segment can be stored in a database. This information can be stored for a single-user or can be combined from a plurality users of the GPS based navigation systems.
摘要翻译：这里公开了一种用于基于全球定位系统（GPS）的导航系统的路线规划方法。该方法识别在基于GPS的导航系统中使用的路线段，并且记录由基于GPS的导航系统旅行的用户行进的至少一个路线段的实际历史旅行时间。实际的旅行历史时间包括基于GPS的导航系统的用户从路线段的开始到路线段的结束所花费的时间量。对于本文的实施例，还记录了路线段被记录的日期和时间。然后，旅行的实际历史时间和路线段的日期和时间可以存储在数据库中。该信息可以存储为单个用户，或可以从基于GPS的导航系统的多个用户组合。

9. 发明授权

US6011383A Low powering apparatus for automatic reduction of power in active and standby modes 失效
标题翻译：用于在主动和待机模式下自动降低功率的低功率设备
公开(公告)号：US6011383A
公开(公告)日：2000-01-04
申请号：US120211
申请日：1998-07-21
申请人： Alvar A. Dean , Kenneth J. Goodnow , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
发明人： Alvar A. Dean , Kenneth J. Goodnow , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1/32 , G05F1/110 , G06F1/00
CPC分类号： G06F1/3296 , G06F1/3203 , Y02B60/1285
摘要： A low powering apparatus for automatic reduction of power in active and standby modes is disclosed. The low powering apparatus includes a state detector, a margins of safety device and a positioning device. The state detector detects a first or second state, such as a standby state and an active state, that has predominated in a recent past. The margins of safety device indicates safe low power margins in correlation to the detected first or second state. The positioning device adjusts the power level according to the outputs of the state detector and margins of safety device. Thus, the low powering apparatus minimizes the power level of a system at the first or second state without compromising full performance of the system.
摘要翻译：公开了一种用于在主动和待机模式下自动降低功率的低功率设备。低功率装置包括状态检测器，安全装置的边缘和定位装置。状态检测器检测在最近过去占主导地位的第一或第二状态，例如待机状态和活动状态。安全装置的边缘表示与检测到的第一或第二状态相关的安全低功率余量。定位装置根据状态检测器的输出和安全装置的余量调整功率水平。因此，低功率设备使系统在第一或第二状态下的功率水平最小化，而不会影响系统的全部性能。

10. 发明授权

US5182468A Current limiting clamp circuit 失效
标题翻译：限流钳位电路
公开(公告)号：US5182468A
公开(公告)日：1993-01-26
申请号：US696380
申请日：1991-05-06
申请人： Charles K. Erdelyi , Mark G. Marshall , John W. Mathews , Patrick E. Perry
发明人： Charles K. Erdelyi , Mark G. Marshall , John W. Mathews , Patrick E. Perry
IPC分类号： H03K5/00 , H03K5/13
CPC分类号： H03K5/131 , H03K5/133 , H03K2005/00195
摘要： A current limiting clamp circuit for providing a clamped voltage at a node and including a P-type MOS transistor and several N-type MOS transistors which are connected in series between the drain of the P-type MOS transistor and ground, with one of the N-type transistors having its gate and drain connected to the drain of the P-type transistor, and having its source connected to the node. In another embodiment, the current limiting clamp circuit includes a pair of P-type transistors and several N-type transistors, with one of the P-type transistors having its source connected to a power supply, its gate connected to ground and its drain connected to the source of the other P-type transistor which has its gate and drain connected to the node.
摘要翻译：一种用于在节点处提供钳位电压并且包括P型MOS晶体管和串联在P型MOS晶体管的漏极和地之间的若干N型MOS晶体管的限流钳位电路，其中一个其栅极和漏极的N型晶体管连接到P型晶体管的漏极，并且其源极连接到节点。在另一个实施例中，限流钳位电路包括一对P型晶体管和若干N型晶体管，其中一个P型晶体管的源极连接到电源，其栅极连接到地，其漏极连接到其栅极和漏极连接到节点的另一个P型晶体管的源极。

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