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1. 发明授权

US5873053A On-chip thermometry for control of chip operating temperature 失效
标题翻译：用于芯片工作温度的片上测温
公开(公告)号：US5873053A
公开(公告)日：1999-02-16
申请号：US841967
申请日：1997-04-08
申请人： Wilbur D. Pricer , Wendell P. Noble , John A. Fifield , John E. Gersbach
发明人： Wilbur D. Pricer , Wendell P. Noble , John A. Fifield , John E. Gersbach
IPC分类号： G01K7/01
CPC分类号： G01K7/01 , Y10S323/907
摘要： Temperatures on a chip, including particular regions of a chip are monitored by sensing changes in sub-threshold conduction of a field effect transistor (FET) integrated on the chip due to changes in charge carrier population distribution with temperature therein. Such changes in sub-threshold current with temperature are preferably detected using a current mirror and two FETs with different channel geometry and slightly different gate voltages such that the currents are equal at a specific design temperature. The slightly different gate voltages are conveniently provided by a low current voltage divider with or without on-chip voltage regulation in which resistor ratios can be accurately and repeatably obtained. Variations from that temperature thus yield large current differences and substantial signal swing which improve noise immunity. Hysteresis can be applied to the output (or amplified output) of the current mirror to obtain bistable thermostat-like action. Variant applications provide sensing at plural chip locations (e.g. for sensing temperature gradients and temperatures of autonomously operating portions of the chip) and a plurality of temperatures on the chip. Temperatures thus monitored control implementation of performance enhancing algorithms in regard to the chip.
摘要翻译：通过感测集成在芯片上的场效应晶体管（FET）的亚阈值传导的变化，由于载流子群体分布随温度的变化而监测芯片上包括芯片的特定区域的温度。亚阈值电流随温度的这种变化优选使用电流镜和具有不同通道几何形状和略微不同的栅极电压的两个FET来检测，使得电流在特定设计温度下是相等的。通过具有或不具有片内电压调节的低电流分压器可以方便地提供略微不同的栅极电压，其中可以精确和重复地获得电阻器比率。因此，该温度的变化产生大的电流差异和显着的信号摆动，这提高了抗噪声性。迟滞可应用于电流镜的输出（或放大输出），以获得双稳态恒温器状作用。变体应用提供在多个芯片位置处的感测（例如用于感测芯片的自主操作部分的温度梯度和温度）以及芯片上的多个温度。因此监控的温度控制了关于芯片的性能增强算法的实现。

2. 发明授权

US4675559A Differential circuit having a high voltage switch 失效
标题翻译：差分电路具有高压开关
公开(公告)号：US4675559A
公开(公告)日：1987-06-23
申请号：US628878
申请日：1984-07-09
申请人： Peter E. Cottrell , John E. Gersbach , Wilbur D. Pricer
发明人： Peter E. Cottrell , John E. Gersbach , Wilbur D. Pricer
IPC分类号： H03K5/02 , H03K17/16 , H03K19/003
CPC分类号： H03K5/02
摘要： This invention provides a differential circuit having first and second transistors interconnected by a third transistor which is symmetrically constructed. A current source is selectively connected to the base of the third transistor. When the current source is connected to the base of the third transistor, the third transistor is saturated, forming a very low impedance path between the first and second transistors. However, when the current source is disconnected from the base of the third transistor, the third transistor impedes the voltage breakdown path between the bases of the first and second transistors. The differential circuit is particularly useful in an improved compact magnetic media system wherein both the stored signal and the write signal or voltage are applied to the bases of the first and second transistor of the circuit without the high write voltages destroying the high performance first and second transistors.
摘要翻译：本发明提供一种差分电路，其具有通过对称构造的第三晶体管互连的第一和第二晶体管。电流源选择性地连接到第三晶体管的基极。当电流源连接到第三晶体管的基极时，第三晶体管饱和，在第一和第二晶体管之间形成非常低的阻抗路径。然而，当电流源与第三晶体管的基极断开时，第三晶体管阻止第一和第二晶体管的基极之间的电压击穿路径。差分电路在改进的小型磁介质系统中特别有用，其中存储的信号和写入信号或电压都被施加到电路的第一和第二晶体管的基极，而没有高写入电压破坏高性能的第一和第二晶体管。

3. 发明授权

US4477846A Sensitive amplifier having a high voltage switch 失效
标题翻译：具有高电压开关的敏感放大器
公开(公告)号：US4477846A
公开(公告)日：1984-10-16
申请号：US332403
申请日：1981-12-21
申请人： Peter E. Cottrell , John E. Gersbach , Wilbur D. Pricer
发明人： Peter E. Cottrell , John E. Gersbach , Wilbur D. Pricer
IPC分类号： H03F3/343 , H03F3/34 , H03F3/347 , H03F3/72 , H03K5/02 , G11B5/09 , G11B5/02
CPC分类号： H03K5/02
摘要： This invention provides an amplifier circuit having first and second transistors interconnected by a third transistor which is symmetrically constructed. A current source is selectively connected to the base of the third transistor. When the current source is connected to the base of the third transistor, the third transistor is saturated, forming a very low impedance path between the first and second transistors. However, when the current source is disconnected from the base of the third transistor, the third transistor impedes the voltage breakdown path between the bases of the first and second transistors. The amplifier circuit is particularly useful in an improved compact magnetic media system wherein both the stored signal and the write signal or voltage are applied to the bases of the first and second transistor of the amplifier without the high write voltages destroying the high performance first and second transistors.
摘要翻译：本发明提供一种放大器电路，其具有通过对称构造的第三晶体管互连的第一和第二晶体管。电流源选择性地连接到第三晶体管的基极。当电流源连接到第三晶体管的基极时，第三晶体管饱和，在第一和第二晶体管之间形成非常低的阻抗路径。然而，当电流源与第三晶体管的基极断开时，第三晶体管阻止第一和第二晶体管的基极之间的电压击穿路径。放大器电路在改进的小型磁介质系统中特别有用，其中存储的信号和写入信号或电压都被施加到放大器的第一和第二晶体管的基极，而没有高写入电压破坏高性能的第一和第二晶体管。

4. 发明授权

US06879638B1 Method and apparatus for providing communication between electronic devices 失效
标题翻译：用于在电子设备之间提供通信的方法和装置
公开(公告)号：US06879638B1
公开(公告)日：2005-04-12
申请号：US09473935
申请日：1999-12-28
申请人： Claude L. Bertin , Anthony R. Bonaccio , John A. Fifield , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , John A. Fifield , Wilbur D. Pricer , William R. Tonti
IPC分类号： H04L25/49 , H04L27/10
CPC分类号： H04L25/4906 , H04L25/4902
摘要： A method and system for providing communication between electronic devices that uses the phase of data transmitted between the devices to indicate logical one and zero values. The method and system has the added benefit of relieving the traditional limitations of voltage communication restraints between devices having differing core voltages (i.e. Differing generations).
摘要翻译：一种用于在电子设备之间提供通信的方法和系统，其使用在设备之间传输的数据的相位来指示逻辑1和零值。该方法和系统具有减轻在具有不同核心电压的器件（即不同代）之间的电压通信约束的传统限制的附加益处。

5. 发明授权

US06496037B1 Automatic off-chip driver adjustment based on load characteristics 有权
标题翻译：基于负载特性的自动片外驱动器调整
公开(公告)号：US06496037B1
公开(公告)日：2002-12-17
申请号：US09588202
申请日：2000-06-06
申请人： Claude L. Bertin , John A. Fifield , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K190175
CPC分类号： H03K19/0005
摘要： An automatic driver adjuster and methods using the same are provided that modify off-chip drivers based on load characteristics. The preferred embodiments are preferably automatic and require little or no human intervention. Preferred embodiments of the current invention analyze and determine the impedance of a node and adjust a number of output drivers in response to the impedance of the node, or analyze a resultant waveform of the node, caused by an input waveform, and adjust a number of output drivers in response to the resultant waveform of the node.
摘要翻译：提供了一种自动驱动器调节器及其使用方法，其基于负载特性修改片外驱动器。优选的实施方案优选是自动的，并且需要很少的或不需要人为干预。本发明的优选实施例分析和确定节点的阻抗并且响应于节点的阻抗调整输出驱动器的数量，或者分析由输入波形引起的节点的合成波形，并且调整多个输出驱动器响应于该结点的合成波形。

6. 发明授权

US06281731B1 Control of hysteresis characteristic within a CMOS differential receiver 有权
标题翻译：控制CMOS差分接收器内的滞后特性
公开(公告)号：US06281731B1
公开(公告)日：2001-08-28
申请号：US09428639
申请日：1999-10-27
申请人： John A. Fifield , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
发明人： John A. Fifield , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K3297
CPC分类号： H03K3/3565 , H03K3/02337
摘要： A differential receiver has a switching point accurately set according to a reference voltage, which switching point is dynamically modified, that is, dc hysteresis is provided, by a circuit internal to the differential receiver. Positioning of the resultant hysteresis characteristic about the reference signal is adjusted by establishing a backgate voltage differential between an input transistor and a reference transistor of the differential receiver. A switching circuit is also provided for controlling switching of a hysteresis circuit at the reference signal plus or minus a desired offset. The switching circuit is gated by an output signal of the input transistor.
摘要翻译：差分接收器具有根据参考电压精确设置的开关点，通过差分接收器内部的电路动态地修改切换点，即提供直流滞后。通过在差分接收器的输入晶体管和参考晶体管之间建立背栅电压差来调整所产生的关于参考信号的滞后特性的定位。还提供了一种开关电路，用于控制滞后电路在参考信号加或减所需偏移的切换。开关电路由输入晶体管的输出信号选通。

7. 发明授权

US06802033B1 Low-power critical error rate communications controller 失效
标题翻译：低功率关键错误率通信控制器
公开(公告)号：US06802033B1
公开(公告)日：2004-10-05
申请号：US09286855
申请日：1999-04-06
申请人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1100
CPC分类号： G06F11/10 , H04L1/0053
摘要： A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.
摘要翻译：一种在通信控制器上动态修改错误恢复的方式，以在当前错误率条件允许的最低功耗模式下工作。当操作条件良好并且检测到少量错误时，输入低功率错误检测/校正模式，从而节省电池寿命。低功率误差校正机构运行频率较低，功率低于大功率机构，并为控制器保持相同的数据速率，从而节省功耗。选择控制器错误（电源）模式可以是外部的，例如当语音数据太嘈杂时，人们在蜂窝电话上使用控制拨盘。或者，选择可以是自动的，在内部进行选择的关键误差电平检测器。

8. 发明授权

US06645789B2 On chip alpha-particle detector 失效
公开(公告)号：US06645789B2
公开(公告)日：2003-11-11
申请号：US10246136
申请日：2002-09-18
申请人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
发明人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
IPC分类号： H01L2100
CPC分类号： H01L27/14683 , G01T1/244 , H01L27/14659 , H01L31/115 , H01L31/118
摘要： An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.

9. 发明授权

US06548338B2 Integrated high-performance decoupling capacitor and heat sink 失效
标题翻译：集成高性能去耦电容和散热片
公开(公告)号：US06548338B2
公开(公告)日：2003-04-15
申请号：US09764504
申请日：2001-01-17
申请人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
发明人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L23/3672 , H01L23/3735 , H01L27/0805 , H01L2924/0002 , H01L2924/10158 , H01L2924/00
摘要： A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.
摘要翻译：一种显着且非常有效的去耦电容器和散热器组合，其在单个结构中提供散热器和去耦电容器，其紧邻芯片上的有源电路，需要散热或去耦电容或两者兼有。这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现，所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路，需要这种去耦电容和散热能力。去耦电容可以使用芯片本身的衬底作为电容板之一，并且形成金属沉积物作为第二电容板，其也用作形成在芯片中的有源电路的散热器。因此，该结构提供了重要且有效的去耦电容，其紧邻芯片上的有源电路，需要这种去耦电容，并为解耦的有源电路提供改进的散热。

10. 发明授权

US06532520B1 Method and apparatus for allocating data and instructions within a shared cache 失效
标题翻译：用于在共享缓存内分配数据和指令的方法和装置
公开(公告)号：US06532520B1
公开(公告)日：2003-03-11
申请号：US09394965
申请日：1999-09-10
申请人： Alvar A. Dean , Marc R. Faucher , John W. Goetz , Kenneth J. Goodnow , Paul T. Gutwin , Stephen W. Mahin , Wilbur D. Pricer
发明人： Alvar A. Dean , Marc R. Faucher , John W. Goetz , Kenneth J. Goodnow , Paul T. Gutwin , Stephen W. Mahin , Wilbur D. Pricer
IPC分类号： G06F1200
CPC分类号： G06F12/121 , G06F12/127 , G06F2212/1021 , G06F2212/6042
摘要： A method and apparatus are provided for managing cache allocation for a plurality of data types in a unified cache having dynamically allocable lines for first type data and for second type data. Cache allocation is managed by counting misses to first type data and misses to second type data in the unified cache, and by determining when a difference between a number of first type data misses and a number of second type data misses crosses a preselected threshold. A replacement algorithm of the unified cache then is adjusted in response to the detected crossing of the preselected threshold, the adjusting step including increasing a replacement priority of the first type data lines in the cache. The replacement algorithm preferably is an LRU algorithm wherein the adjusting step includes incrementing an age indication of the first type data lines. Hardware for implementing the inventive cache allocation management method comprises a miss counter configured to increment its count in response to a miss to first type data signal on a first counter input and to output a first logic state on a first counter output when the counter's count exceeds a first predetermined count. A priority adjustment circuit coupled to the first counter output increases the replacement priority of the first type data relative to the replacement priority of the second type data in response to the first logic state output by the miss counter.
摘要翻译：提供了一种方法和装置，用于管理具有用于第一类型数据和第二类型数据的动态可分配行的统一高速缓存中的多个数据类型的高速缓存分配。高速缓存分配通过对统一高速缓存中的第一类型数据和第二类型数据的丢失进行计数，并且通过确定多个第一类型数据丢失与多个第二类型数据丢失之间的差异何时穿过预选阈值来管理高速缓存分配。然后，响应于检测到的预选阈值的交叉，调整统一高速缓存的替换算法，该调整步骤包括增加高速缓存中的第一类型数据线的替换优先级。替换算法优选地是LRU算法，其中调整步骤包括递增第一类型数据线的年龄指示。用于实现本发明的高速缓存分配管理方法的硬件包括错误计数器，其配置为响应于第一计数器输入上的第一类型数据信号的未命中而增加其计数，并且当计数器的计数超过时，在第一计数器输出上输出第一逻辑状态第一预定计数。耦合到第一计数器输出的优先级调整电路响应于未命中计数器输出的第一逻辑状态，增加第一类型数据相对于第二类型数据的替换优先级的替换优先级。

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