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    • 13. 发明授权
    • Memory test apparatus and testing method
    • 记忆测试仪器及测试方法
    • US08345496B2
    • 2013-01-01
    • US12990983
    • 2009-05-07
    • Takashi Nakamura
    • Takashi Nakamura
    • G11C29/00
    • G11C29/56G11C11/401G11C29/50016G11C29/56012
    • A refresh control circuit receives an interrupt signal, which is a request to refresh DRAM (Dynamic Random Access Memory) and which is asserted at predetermined timings. The refresh control circuit counts the number of times the interrupt signal is asserted, and asserts an interrupt subroutine start signal, which is an instruction to refresh the DRAM, in an idle state in which the DRAM is accessible from an external circuit, for a number of times that is equal to the number of times thus counted. When the interrupt subroutine start signal is asserted, a refresh circuit executes a predetermined interrupt subroutine, and supplies a refresh pattern to the DRAM.
    • 刷新控制电路接收中断信号,该中断信号是刷新DRAM(动态随机存取存储器)的请求,并且以预定的定时被断言。 刷新控制电路对中断信号被断言的次数进行计数,并且在可从外部电路访问DRAM的空闲状态下断言作为刷新DRAM的指令的中断子程序开始信号,数量 的次数等于这样计算的次数。 当中断子程序启动信号被断言时,刷新电路执行预定的中断子程序,并向DRAM提供刷新模式。
    • 14. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    • 半导体集成电路设备
    • US20120319738A1
    • 2012-12-20
    • US13579766
    • 2010-02-19
    • Takashi NakamuraKosuke Yayama
    • Takashi NakamuraKosuke Yayama
    • H03L7/00
    • H03L1/022H03L7/00
    • A frequency-voltage converting circuit 13 is composed of a switch unit including switches SW1 and SW2, electrostatic capacitive elements C and C10 to C13, and switches CSW0 to CSW3. The electrostatic capacitive elements C10 to C13 are composed of elements having mutually different absolute values of capacitance and are provided so as to cover a frequency range intended by a designer. The electrostatic capacitance values are weighted by, for example, 2. The electrostatic capacitive elements C11 to C13 are selected by, for example, the switches CSW0 to CSW3 based on 4-bit frequency adjustment control signals SELC0 to SELC3, thereby carrying out frequency switching.
    • 频率电压转换电路13由包括开关SW1和SW2,静电电容元件C和C10至C13的开关单元,以及开关CSW0至CSW3组成。 静电电容元件C10至C13由具有相互不同的电容绝对值的元件组成,并且被设置为覆盖由设计者预期的频率范围。 静电电容值通过例如2进行加权。静电电容元件C11至C13通过例如基于4位频率调整控制信号SELC0至SELC3的开关CSW0至CSW3来选择,从而进行频率切换 。
    • 15. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20120161868A1
    • 2012-06-28
    • US13333448
    • 2011-12-21
    • Kosuke YAYAMATakashi Nakamura
    • Kosuke YAYAMATakashi Nakamura
    • H03F3/45
    • H03L7/00H03K3/0231H03L1/00H03L1/022
    • A clock signal capable of changing the frequency in a wide range and with high resolution is generated.An operational amplifier AMP1 is subject to feedback control so that the voltage of a positive input part equals that of a negative input part. The voltage of a circuit node fbck equals a reference voltage VREFI. A decoder DEC decodes control signals CNT7 and CNT6 and turns on one of transistors T2 to T5. This configuration provides feedback control so that the voltage of the circuit node fbck equals the reference voltage VREFI. This significantly reduces the on-resistances of the transistors T2 to T5 and prevents the degradation of the frequency accuracy.
    • 产生能够在宽范围内以高分辨率改变频率的时钟信号。 运算放大器AMP1经受反馈控制,使得正输入部分的电压等于负输入部分的电压。 电路节点fbck的电压等于参考电压VREFI。 解码器DEC解码控制信号CNT7和CNT6,并导通晶体管T2至T5中的一个。 该配置提供反馈控制,使得电路节点fbck的电压等于参考电压VREFI。 这显着地降低了晶体管T2至T5的导通电阻并防止了频率精度的降低。
    • 16. 发明授权
    • Iron-type golf club set
    • 铁型高尔夫球杆套装
    • US08012036B2
    • 2011-09-06
    • US12502131
    • 2009-07-13
    • Takashi Nakamura
    • Takashi Nakamura
    • A63B53/04
    • A63B53/047A63B53/00A63B60/00A63B2053/005A63B2053/0408A63B2053/0445
    • A set of iron-type golf clubs comprising “n” pieces of golf clubs having club heads with different loft angles and having advantages that variation in spin amount at mis-shots by long irons is small and accuracy in shots of intentionally curving a ball by short irons is high, each of the club heads having face 4 provided with a plurality of face grooves 10 extending in the toe-heel direction and a plurality of auxiliary grooves 11 including a plurality of first auxiliary grooves 11a extending in at least a region between toe side line L1 and heel side line L2, the first auxiliary grooves 11a being, in this region, in the form of curved grooves convex upward such that a curve descends from peak 13 toward the toe and heel side lines L1 and L2, and average degrees of curvature θi of the first auxiliary grooves of the club heads satisfying a specific relationship.
    • 一组铁杆式高尔夫球杆,包括具有不同杆角的球杆头的“n”个高尔夫球杆,并且具有以下优点,即长铁杆误射时的旋转量的变化小,故意将球弯曲的精确度 短铁杆较高,每个球杆头具有设置有沿趾部跟随方向延伸的多个面槽10的面4,以及多个辅助槽11,其包括多个第一辅助槽11a,第一辅助槽11a至少在 脚趾侧线L1和脚跟侧线L2,在该区域中,第一辅助槽11a呈向上凸起的曲线形状,使得曲线从峰13向脚趾和脚跟侧线L1和L2下降,并且平均 曲率角度;第一个辅助槽的第一个,满足特定的关系。
    • 17. 发明申请
    • HOT DRY ROCK GENERATION SYSTEM
    • 热干燥生成系统
    • US20110187126A1
    • 2011-08-04
    • US13057676
    • 2009-02-23
    • Takashi NakamuraKoji HiramotoIchiro NakajoYoshiyuki Yokohama
    • Takashi NakamuraKoji HiramotoIchiro NakajoYoshiyuki Yokohama
    • H02K7/18
    • F03G7/04
    • A hot dry rock generation system, having: a recharge well that is formed from the ground to an underground hot dry rock into which a heat carrier streams through the recharge well; a production well that is formed from the underground hot dry rock from which the heated heat carrier is streams through the production well; a power generation plant that converts the thermal energy of the heat carrier streaming out of, into electric energy; a collecting tank that stores the heat carrier discharged from the power generation plant; a sealing water pump that sucks the heat carrier collected in the collecting tank and makes the heat carrier stream into the recharge well, whereby the hot dry rock generation system is provided with a heat exchanger into which the heat carrier streaming out of the production well streams.
    • 一种热干燥岩石发生系统,具有:从地面到地下热干燥岩石形成的补给井,热载体流过补给井; 由加热的热载体从生产井流出的地下热干燥岩石形成的生产井; 将热载体的热能转换成电能的发电厂; 存储从发电厂排出的热载体的收集罐; 密封水泵吸收收集在收集罐中的热载体并使热载体流进入补给井,由此热干燥岩石产生系统设置有热交换器,热载体从生产井流中流出 。
    • 20. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US07888981B2
    • 2011-02-15
    • US12851597
    • 2010-08-06
    • Kazuo YamakidoTakashi Nakamura
    • Kazuo YamakidoTakashi Nakamura
    • H03L7/06
    • H03L7/0995H03L7/085H03L7/093H03L2207/50
    • The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.
    • 半导体集成电路包括具有可操作以产生时钟信号的数字控制信号产生部分和数字控制部分的时钟产生部分。 时钟产生部分还包括相位频率比较器和控制寄存器。 比较器被提供有参考信号CLKin和反馈信号。 控制寄存器提供比较器的输出信号,并存储两个或更多位的数字控制信息。 时钟产生部分还包括用于预先存储用于锁定操作的初始设置数据集合的控制数据存储电路。 响应于操作选择信息,初始设定数据被存储在来自控制数据存储电路的控制寄存器的高位。 因此,可以减少将控制信息存储在用于数字控制时钟信号产生部分的寄存器中的步骤数。