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11. 发明申请

US20140218266A1 Display Method, Terminal Device And Multi-Terminal Device System 有权
标题翻译：显示方式，终端设备和多终端设备系统
公开(公告)号：US20140218266A1
公开(公告)日：2014-08-07
申请号：US14342669
申请日：2012-09-04
申请人： Dong Chen , Qiang Zhang , Yingfeng Ma , Zhifeng Xin
发明人： Dong Chen , Qiang Zhang , Yingfeng Ma , Zhifeng Xin
IPC分类号： G06F3/14
CPC分类号： G06F3/048 , G06F1/1616 , G06F1/1654 , G06F1/1692 , G06F3/1446 , G06F3/1454 , G06F2200/1614 , G09G2354/00 , G09G2356/00
摘要： Disclosed are a display method, a terminal device and a multi-terminal device system. The display method is applied to a first terminal device and the first terminal device includes a first display unit. The method includes the first display unit displaying a first display interface; detecting a connection with a second terminal device, and obtaining a detection result, the second terminal device including a second display unit displaying a second display interface, and when the detection result indicating that the first terminal device and the second terminal device are connected, one of the first display unit and the second display unit displaying the first display interface, and the other of the first display unit and the second display unit displaying a third display interface, the third display interface and the first display interface being different.
摘要翻译：公开了一种显示方法，终端装置和多终端装置系统。显示方法应用于第一终端装置，第一终端装置包括第一显示单元。该方法包括显示第一显示界面的第一显示单元; 检测与第二终端设备的连接，并获得检测结果，所述第二终端设备包括显示第二显示界面的第二显示单元，当连接了所述第一终端设备和所述第二终端设备的检测结果时，所述第一显示单元和所述第二显示单元显示所述第一显示界面，所述第一显示单元和所述第二显示单元中的另一个显示第三显示界面，所述第三显示界面和所述第一显示界面不同。

12. 发明授权

US08791813B2 Monitoring system for testing apparatus 有权
标题翻译：检测仪器监控系统
公开(公告)号：US08791813B2
公开(公告)日：2014-07-29
申请号：US13478264
申请日：2012-05-23
申请人： Dong Chen
发明人： Dong Chen
IPC分类号： G08B29/00
CPC分类号： G01R31/2844 , G01R1/025
摘要： A monitoring system includes a testing apparatus and a display control apparatus connected to the testing apparatus. The testing apparatus includes a plurality of testing locations and a collection module connected to the plurality of testing locations. Each of the plurality of testing locations receives a tested product, which is tested by the testing apparatus. The collection module collects testing states of the tested products. A display apparatus is connected to the display control apparatus. The display control apparatus controls the display apparatus to show a plurality of indicating blocks corresponding to the plurality of testing locations. The display apparatus is adapted to display the plurality of indicating blocks to match the plurality of testing locations. The display control apparatus controls each of the plurality of indicating blocks to show the testing state of the tested product in each the plurality of testing locations.
摘要翻译：监视系统包括连接到测试装置的测试装置和显示控制装置。测试装置包括多个测试位置和连接到多个测试位置的收集模块。多个测试位置中的每一个接收测试产品，由测试装置测试。收集模块收集测试产品的测试状态。显示装置连接到显示控制装置。显示控制装置控制显示装置显示与多个测试位置对应的多个指示块。显示装置适于显示多个指示块以匹配多个测试位置。显示控制装置控制多个指示块中的每一个以显示多个测试位置中的每个测试产品的测试状态。

13. 发明授权

US08782164B2 Implementing asyncronous collective operations in a multi-node processing system 有权
标题翻译：在多节点处理系统中实现异步集体操作
公开(公告)号：US08782164B2
公开(公告)日：2014-07-15
申请号：US12697043
申请日：2010-01-29
申请人： Dong Chen , Noel A. Eisley , Philp Heidelberger , Sameer Kumar , Valentina Salapura , Burkhard Steinmacher-Burow
发明人： Dong Chen , Noel A. Eisley , Philp Heidelberger , Sameer Kumar , Valentina Salapura , Burkhard Steinmacher-Burow
IPC分类号： G06F15/16 , G06F12/00
CPC分类号： G06F15/16
摘要： A method, system, and computer program product are disclosed for implementing an asynchronous collective operation in a multi-node data processing system. In one embodiment, the method comprises sending data to a plurality of nodes in the data processing system, broadcasting a remote get to the plurality of nodes, and using this remote get to implement asynchronous collective operations on the data by the plurality of nodes. In one embodiment, each of the nodes performs only one task in the asynchronous operations, and each nodes sets up a base address table with an entry for a base address of a memory buffer associated with said each node. In another embodiment, each of the nodes performs a plurality of tasks in said collective operations, and each task of each node sets up a base address table with an entry for a base address of a memory buffer associated with the task.
摘要翻译：公开了一种在多节点数据处理系统中实现异步集体操作的方法，系统和计算机程序产品。在一个实施例中，该方法包括向数据处理系统中的多个节点发送数据，向多个节点广播远程获取，并且使用该远程获取来对多个节点对数据执行异步集合操作。在一个实施例中，每个节点在异步操作中仅执行一个任务，并且每个节点建立具有与所述每个节点相关联的存储器缓冲器的基地址的条目的基地址表。在另一实施例中，每个节点在所述集体操作中执行多个任务，并且每个节点的每个任务用与用于与任务相关联的存储器缓冲器的基地址的条目建立基地址表。

14. 发明申请

US20140162404A1 METHOD FOR PACKAGING LOW-K CHIP 有权
标题翻译：用于包装低K芯片的方法
公开(公告)号：US20140162404A1
公开(公告)日：2014-06-12
申请号：US14233461
申请日：2011-10-21
申请人： Li Zhang , Zhiming Lai , Dong Chen , Jinhui Chen
发明人： Li Zhang , Zhiming Lai , Dong Chen , Jinhui Chen
IPC分类号： H01L23/00
CPC分类号： H01L23/49582 , H01L21/561 , H01L21/568 , H01L23/3107 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/95 , H01L24/96 , H01L2224/02379 , H01L2224/03334 , H01L2224/0382 , H01L2224/0391 , H01L2224/0401 , H01L2224/04105 , H01L2224/05005 , H01L2224/05541 , H01L2224/05558 , H01L2224/05569 , H01L2224/05572 , H01L2224/12105 , H01L2224/13006 , H01L2224/13023 , H01L2224/131 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81815 , H01L2224/83192 , H01L2224/94 , H01L2924/00014 , H01L2924/0002 , H01L2924/12042 , H01L2924/15311 , H01L2924/15788 , H01L2924/00012 , H01L2924/014 , H01L2224/05552 , H01L2224/03 , H01L2224/11 , H01L2924/00
摘要： Provided is a method for packaging a low-k chip, comprising: attaching onto a carrier wafer a layer of temporary strippable film; arranging inversely a chip (2-1) onto the carrier wafer via the temporary strippable film; attaching thin film layer I (2-4) onto the carrier wafer for packaging; bonding a support wafer (2-5) onto the thin film layer I (2-4) and solidifying; forming a reconstructed wafer consisting of the chip (2-1), thin film layer I (2-4), and the support wafer; detaching the reconstructed wafer from the carrier wafer; completing a rewired metal wiring (2-6) on thin film layer I (2-4); forming a metal column (2-7) at an end of the rewired metal wiring (2-6); attaching thin film layer II (2-8) onto a surface of the metal column (2-7), packaging, and solidifying; coating a metal layer (2-9) on the top of the metal column (2-7), forming BGA solder balls (2-10) on the metal layer (2-9) by means of printing or ball planting; and finally slicing into individual BGA packages the reconstructed wafer having formed the BGA solder balls (2-10).
摘要翻译：提供了一种用于封装低k芯片的方法，包括：将一层临时剥离膜附着在载体晶片上; 通过临时可剥离膜将芯片（2-1）反向布置在载体晶片上; 将薄膜层I（2-4）附着在载体晶片上进行包装; 将支撑晶片（2-5）接合到薄膜层I（2-4）上并固化; 形成由芯片（2-1），薄膜层I（2-4）和支撑晶片组成的重构晶片; 将重建的晶片从载体晶片分离; 在薄膜层I（2-4）上完成重新布线的金属布线（2-6）; 在重新布线的金属布线（2-6）的一端形成金属柱（2-7）; 将薄膜层II（2-8）附着到金属柱（2-7）的表面上，包装和固化; 在金属柱（2-7）的顶部涂覆金属层（2-9），通过印刷或球面种植在金属层（2-9）上形成BGA焊球（2-10）; 最后将形成BGA焊球（2-10）的重构晶片切割成单独的BGA封装。

15. 发明申请

US20140065325A1 SEALANT COMPOSITION, METHOD FOR PREVENTING LIQUID CRYSTAL CONTAMINATION, LIQUID CRYSTAL PANEL AND DISPLAY DEVICE 有权
标题翻译：密封组合物，预防液晶污染的方法，液晶面板和显示装置
公开(公告)号：US20140065325A1
公开(公告)日：2014-03-06
申请号：US13995318
申请日：2012-12-21
申请人： Renwei Guo , Dong Chen
发明人： Renwei Guo , Dong Chen
IPC分类号： C09D133/14 , G02F1/1339
CPC分类号： C09D133/14 , B32B2457/202 , C08F220/18 , C08F222/1006 , C09J4/06 , C09J133/062 , C09K3/10 , C09K2003/1062 , C09K2200/0625 , G02F1/1339 , Y10T428/1059 , Y10T428/1082
摘要： Disclosed is a sealant composition, a liquid crystal device and a method for preventing liquid crystal contamination using the sealant composition. The sealant composition consists of 20-30 parts by weight of an ultraviolet polymerizable double bond monomer, 15-20 parts by weight of a heat polymerization monomer, 5-20 parts by weight of a polymerizable oligomer, 0.1-5 parts by weight of a photoinitiator, 10-20 parts by weight of a heat curing agent and 0-20 parts by weight of a particulate additive, wherein said polymerizable oligomer is poly(ethylene glycol) diacrylate or derivatives thereof. Through the reaction between the polymerizable oligomers and the polymer of the ultraviolet polymerizable double bond monomers to generate a reticular high molecular polymer, the anchoring effect of the polymer on the surrounding unreacted heat polymerization monomers is effectively enhanced, thereby reducing the contamination of the crystal liquid by the sealant.
摘要翻译：公开了一种密封剂组合物，液晶装置和使用密封剂组合物防止液晶污染的方法。密封剂组合物由20-30重量份的紫外线可聚合双键单体，15-20重量份的热聚合单体，5-20重量份的聚合性低聚物，0.1-5重量份的光引发剂，10-20重量份热固化剂和0-20重量份颗粒添加剂，其中所述可聚合低聚物是聚（乙二醇）二丙烯酸酯或其衍生物。通过可聚合低聚物和紫外线可聚合双键单体的聚合物之间的反应以产生网状高分子聚合物，聚合物对周围未反应的热聚合单体的锚固效果被有效地提高，从而减少了结晶液体的污染由密封胶。

16. 发明授权

US08667049B2 Massively parallel supercomputer 有权
标题翻译：大容量并行超级计算机
公开(公告)号：US08667049B2
公开(公告)日：2014-03-04
申请号：US13566024
申请日：2012-08-03
申请人： Matthias A. Blumrich , Dong Chen , George L. Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampap , Philip Heidlberger , Gerard V. Kopcsay , Lawrence S. Mok , Todd E. Takken
发明人： Matthias A. Blumrich , Dong Chen , George L. Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampap , Philip Heidlberger , Gerard V. Kopcsay , Lawrence S. Mok , Todd E. Takken
IPC分类号： G06F15/173
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.
摘要翻译：数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构，即每个处理节点包括单个专用集成电路（ASIC）。在每个ASIC节点内是多个处理元件，每个处理元件由中央处理单元（CPU）和多个浮点处理器组成，以实现计算性能，封装密度，低成本以及功率和冷却要求的最佳平衡。单个节点内的多个处理器单独或同时工作在要解决的特定算法所要求的计算或通信的任何组合上。片上系统ASIC节点通过多个独立网络互连，从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。多个网络包括用于并行算法消息传递的三个高速网络，包括Torus，全局树和提供全局障碍和通知功能的全球异步网络。

17. 发明申请

US20140044015A1 T-STAR INTERCONNECTION NETWORK TOPOLOGY 审中-公开
标题翻译： T-STAR互联网络拓扑
公开(公告)号：US20140044015A1
公开(公告)日：2014-02-13
申请号：US13584300
申请日：2012-08-13
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
IPC分类号： H04L12/28
CPC分类号： H04L41/0663 , H04L41/12 , H04L41/145 , H04L45/04
摘要： According to one embodiment of the present invention, a method of constructing network communication for a grid of node groups is provided, the grid including an M dimensional grid, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one, wherein each node includes a router. The method includes directly connecting each node in each node group to every other node in the node group via intra-group links and directly connecting each node in each node group of the M dimensional grid to a node in each neighboring node group in the M dimensional grid via inter-group links.
摘要翻译：根据本发明的一个实施例，提供了一种为节点组网格构建网络通信的方法，所述网格包括M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N 大于1，其中每个节点包括路由器。该方法包括通过组内链路将每个节点组中的每个节点直接连接到节点组中的每个其他节点，并将M维网格的每个节点组中的每个节点直接连接到M维中的每个相邻节点组中的节点网格通过组间链接。

18. 发明授权

US08626957B2 Collective network for computer structures 有权
标题翻译：计算机结构集体网络
公开(公告)号：US08626957B2
公开(公告)日：2014-01-07
申请号：US13101566
申请日：2011-05-05
申请人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd E. Takken , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd E. Takken , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
IPC分类号： G06F15/16
CPC分类号： H04L1/08 , G06F9/46 , G06F11/08 , G06F11/1423 , H03M13/09 , H04L1/0061 , H04L1/1607 , H04L1/1867 , H04L2001/0093 , H04L2001/0097
摘要： A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
摘要翻译：一种用于实现互连处理节点之间的高速，低延迟全局集体通信的系统和方法。全局集体网络最优地使得能够在具有多个互连处理节点的计算机结构中执行并行算法操作期间执行集体缩减操作。包括通过链路互连网络节点的路由器设备，以便于在虚拟网络的节点处执行低延迟全局处理操作。全局集体网络可以被配置为以异步或同步方式提供全局屏障和中断功能。当在大规模并行超级计算结构中实现时，全局集体网络根据处理算法的需要在物理上和逻辑上可分割。

19. 发明授权

US08595554B2 Reproducibility in a multiprocessor system 有权
标题翻译：多处理器系统中的重现性
公开(公告)号：US08595554B2
公开(公告)日：2013-11-26
申请号：US12774475
申请日：2010-05-05
申请人： Ralph A. Bellofatto , Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Thomas A. Liebsch , Martin Ohmacht , Don D. Reed , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Ralph A. Bellofatto , Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Thomas A. Liebsch , Martin Ohmacht , Don D. Reed , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F11/00
CPC分类号： G06F1/10 , G06F11/2242
摘要： Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.
摘要翻译：如果问题是可重现的，通常会大大帮助解决问题。为了确保多处理器系统的可重复性，提出了以下方面：确定性系统启动状态，单个系统时钟，系统中的时钟相位对齐，全系统同步事件，系统组件的可重复执行，确定性芯片接口，零 - 与系统进行通信，精确地停止系统并扫描系统状态。

20. 发明授权

US08412974B2 Global synchronization of parallel processors using clock pulse width modulation 有权
标题翻译：使用时钟脉宽调制的并行处理器的全局同步
公开(公告)号：US08412974B2
公开(公告)日：2013-04-02
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/04 , G06F1/12 , G06F15/16
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

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