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11. 发明授权

US08082475B2 Enhanced microprocessor interconnect with bit shadowing 有权
标题翻译：增强的微处理器互连与位阴影
公开(公告)号：US08082475B2
公开(公告)日：2011-12-20
申请号：US12165848
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F11/14 , G06F11/30
CPC分类号： G06F11/2007 , G06F11/0724 , G06F11/076 , H04L1/20
摘要： Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译：阴影选择逻辑用于选择驱动程序位位置作为阴影驱动程序值，线路驱动程序可以在总线的单独链路段上传输所选驱动程序位位置和阴影驱动程序值的数据。此外，阴影比较逻辑用于将选定的接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较，并且阴影计数器计数误差相对于总线错误率的速率经过一段时间。响应于在总线错误率的预定义阈值内的错误比较的速率来识别有缺陷的链路段。

12. 发明申请

US20100005202A1 DYNAMIC SEGMENT SPARING AND REPAIR IN A MEMORY SYSTEM 失效
标题翻译：动态部分在记忆系统中的分配和修复
公开(公告)号：US20100005202A1
公开(公告)日：2010-01-07
申请号：US12165809
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Ravi K. Arimilli , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Ravi K. Arimilli , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F3/00
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译：用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段。

13. 发明授权

US08082474B2 Bit shadowing in a memory system 失效
标题翻译：存储系统中的位阴影
公开(公告)号：US08082474B2
公开(公告)日：2011-12-20
申请号：US12165799
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F11/14 , G06F11/30
CPC分类号： G06F11/167 , G06F11/073 , G06F11/076 , G06F11/1004 , G06F11/2007 , G11C5/04 , G11C29/02 , G11C29/022
摘要： Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition, shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare Shadow counters are used to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译：阴影选择逻辑用于选择驱动程序位位置作为阴影驱动程序值，线路驱动程序可以在总线的单独链路段上传输所选驱动程序位位置和阴影驱动程序值的数据。此外，阴影比较逻辑用于将所选接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较阴影计数器用于计算相对于总线错误的误比率率一段时间。响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。

14. 发明申请

US20100005335A1 MICROPROCESSOR INTERFACE WITH DYNAMIC SEGMENT SPARING AND REPAIR 审中-公开
标题翻译：微处理器接口与动态分段交换和修复
公开(公告)号：US20100005335A1
公开(公告)日：2010-01-07
申请号：US12165858
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F11/00 , G06F13/40
CPC分类号： G06F11/2007
摘要： A processing device, system, method, and design structure for providing a microprocessor interface with dynamic segment sparing and repair. The processing device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译：一种处理设备，系统，方法和设计结构，用于提供具有动态段保存和修复的微处理器接口。处理装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段。

15. 发明授权

US07539800B2 System, method and storage medium for providing segment level sparing 有权
标题翻译：系统，方法和存储介质，用于提供段级备份
公开(公告)号：US07539800B2
公开(公告)日：2009-05-26
申请号：US10903188
申请日：2004-07-30
申请人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F13/00 , G06F11/00
CPC分类号： G06F11/201 , G06F11/104
摘要： A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.
摘要翻译：一个内存子系统，包括段级备份。存储器子系统包括具有段级保护的级联互连系统。级联互连系统包括两个或多个存储器组件和存储器总线。存储器总线包括多个段，并且存储器组件经由存储器总线互连。

16. 发明申请

US20090094476A1 DERIVING CLOCKS IN A MEMORY SYSTEM 失效
标题翻译：在记忆系统中传送时钟
公开(公告)号：US20090094476A1
公开(公告)日：2009-04-09
申请号：US12332396
申请日：2008-12-11
申请人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
发明人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
IPC分类号： G06F1/00 , G06F1/06
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method. The method includes receiving a reference oscillator clock at the hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译：提供了一种用于在存储器系统中导出时钟的计算机程序产品和集线器设备。计算机程序产品包括可由处理电路读取的存储介质，并且存储由处理电路执行以便于方法的指令。该方法包括在集线器设备处接收参考振荡器时钟。集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。以基准时钟频率工作的基本时钟从参考振荡器时钟导出。通过将基本时钟乘以存储器乘法器导出存储器接口时钟。控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

17. 发明申请

US20110075740A1 Configurable Differential to Single Ended IO 有权
标题翻译：可配置差分至单端IO
公开(公告)号：US20110075740A1
公开(公告)日：2011-03-31
申请号：US12568765
申请日：2009-09-29
申请人： Frank D. Ferraiolo , Kevin C. Gower , Robert B. Tremaine , Kenneth L. Wright
发明人： Frank D. Ferraiolo , Kevin C. Gower , Robert B. Tremaine , Kenneth L. Wright
IPC分类号： H04B3/00
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译：一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。传输幅度和数据的单端或差分传输是功率模式的例子。控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。

18. 发明授权

US07590882B2 System, method and storage medium for bus calibration in a memory subsystem 失效
标题翻译：用于内存子系统总线校准的系统，方法和存储介质
公开(公告)号：US07590882B2
公开(公告)日：2009-09-15
申请号：US11780556
申请日：2007-07-20
申请人： Frank D. Ferraiolo , Kevin C. Gower
发明人： Frank D. Ferraiolo , Kevin C. Gower
IPC分类号： G06F1/12 , H04L9/18
CPC分类号： G06F13/4239
摘要： A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration.
摘要翻译：具有一个或多个存储器模块的级联互连系统，存储器控制器和利用定期重新校准的存储器总线。存储器模块和存储器控制器通过存储器总线通过分组化的多传输接口直接互连，并提供用于定期重新校准的加扰数据。

19. 发明授权

US06954870B2 Method for receiver delay detection and latency minimization for a source synchronous wave pipelined interface 失效
标题翻译：用于源同步波流水线接口的接收机延迟检测和延迟最小化的方法
公开(公告)号：US06954870B2
公开(公告)日：2005-10-11
申请号：US10096382
申请日：2002-03-12
申请人： Jonathan Y. Chen , Frank D. Ferraiolo , Kevin C. Gower , Patrick J. Meaney , William J. Scarpero, Jr.
发明人： Jonathan Y. Chen , Frank D. Ferraiolo , Kevin C. Gower , Patrick J. Meaney , William J. Scarpero, Jr.
IPC分类号： G06F1/12 , G06F3/00 , H04L7/00 , H04L7/10
CPC分类号： H04L7/10 , H04L7/0008 , H04L7/005
摘要： A method of calibrating an elastic interface is provided to automatically achieve a minimal cycle delay through the interface. An existing self-alignment interface (i.e. elastic interface) is used to de-skew within a cycle and stage the data to have it arrive on a given, programmed target cycle. However, this target cycle must be calculated in advance and may be larger than it needs to be, causing more latency on the interface. This method is used to determine the earliest target cycle (with or without additional guard-band). This target cycle is used to adjust the interface automatically to achieve this earliest target cycle. The determination of earliest target cycle can be done once, continuously, or using a sample window. The method also can be used for interfaces that have frequency multipliers or phase shifts at its boundaries.
摘要翻译：提供校准弹性界面的方法以通过界面自动实现最小的循环延迟。现有的自对准接口（即弹性接口）用于在一个周期内去偏移，并且在给定的编程的目标周期上对数据进行分段以使其达到。但是，这个目标周期必须提前计算，并且可能会大于需要的时间，从而在接口上造成更多的延迟。该方法用于确定最早的目标周期（带或不带附加保护带）。该目标周期用于自动调整接口以实现最早的目标周期。最早的目标周期的确定可以进行一次，连续或使用样本窗口。该方法还可用于在其边界具有频率乘法器或相移的接口。

20. 发明授权

US08139430B2 Power-on initialization and test for a cascade interconnect memory system 失效
标题翻译：级联互连存储器系统的上电初始化和测试
公开(公告)号：US08139430B2
公开(公告)日：2012-03-20
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G11C7/10 , G11C7/18
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译：用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。该接口可在SBC模式和高速模式下工作。存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

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