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1. 发明申请

US20110075740A1 Configurable Differential to Single Ended IO 有权
标题翻译：可配置差分至单端IO
公开(公告)号：US20110075740A1
公开(公告)日：2011-03-31
申请号：US12568765
申请日：2009-09-29
申请人： Frank D. Ferraiolo , Kevin C. Gower , Robert B. Tremaine , Kenneth L. Wright
发明人： Frank D. Ferraiolo , Kevin C. Gower , Robert B. Tremaine , Kenneth L. Wright
IPC分类号： H04B3/00
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译：一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。传输幅度和数据的单端或差分传输是功率模式的例子。控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。

2. 发明授权

US09325534B2 Configurable differential to single ended IO 有权
标题翻译：可配置差分至单端IO
公开(公告)号：US09325534B2
公开(公告)日：2016-04-26
申请号：US12568765
申请日：2009-09-29
申请人： Frank D. Ferraiolo , Kevin C. Gower , Robert B. Tremaine , Kenneth L. Wright
发明人： Frank D. Ferraiolo , Kevin C. Gower , Robert B. Tremaine , Kenneth L. Wright
IPC分类号： H04B3/00 , H04L25/02
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译：一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。传输幅度和数据的单端或差分传输是功率模式的例子。控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。

3. 发明申请

US20100005218A1 ENHANCED CASCADE INTERCONNECTED MEMORY SYSTEM 审中-公开
标题翻译：增强的CASCADE互连存储系统
公开(公告)号：US20100005218A1
公开(公告)日：2010-01-07
申请号：US12165816
申请日：2008-07-01
申请人： Kevin C. Gower , Paul W. Coteus , Warren E. Maule , Robert B. Tremaine
发明人： Kevin C. Gower , Paul W. Coteus , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F12/06
CPC分类号： G06F13/4234
摘要： A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames.
摘要翻译：提供了一种用于提供增强级联互连存储器系统的系统，存储器集线器设备，方法和设计结构。该系统包括存储器控制器，存储器通道，耦合到存储器通道的存储器集线器设备，以经由另一个存储器集线器设备的直接连接和级联互连中的一个与存储器控制器进行通信，以及与存储控制器通信的多个存储器设备存储器控制器经由一个或多个级联互连的存储器集线器设备。存储器通道包括耦合到存储器控制器并且可操作用于传输可配置数据帧的单向下游链路段。存储器通道还包括耦合到存储器控制器并且可操作用于传送数据帧的单向上游链路段。

4. 发明申请

US20080005496A1 Memory Systems for Automated Computing Machinery 有权
标题翻译：自动计算机存储系统
公开(公告)号：US20080005496A1
公开(公告)日：2008-01-03
申请号：US11383989
申请日：2006-05-18
申请人： Daniel M. Dreps , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Daniel M. Dreps , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F13/00
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.
摘要翻译：公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。

5. 发明申请

US20120151171A1 PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY 有权
标题翻译：在具有INDETERMINATE读取数据延迟的存储器系统中提供帧起始指示
公开(公告)号：US20120151171A1
公开(公告)日：2012-06-14
申请号：US13397819
申请日：2012-02-16
申请人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A memory system, having indeterminate read data latency, that includes a memory controller and one or more hub devices. The memory controller is configured for receiving data transfers via an upstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting a frame start indicator. The data frame includes an identification tag that is utilized by the memory controller to associate the data frame with a corresponding read instruction issued by the memory controller. The one or more hub devices are in communication with the memory controller in a cascade interconnect manner via the upstream channel and a downstream channel. Each hub device is configured for receiving the data transfers via the upstream channel or the downstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting the frame start indicator.
摘要翻译：具有不确定的读取数据延迟的存储器系统，其包括存储器控制器和一个或多个集线器设备。存储器控制器被配置为经由上游信道接收数据传输，并且通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。数据帧包括由存储器控制器用于将数据帧与由存储器控制器发出的相应读取指令相关联的识别标签。一个或多个集线器设备经由上游信道和下游信道以级联互连方式与存储器控制器通信。每个集线器设备被配置用于经由上游信道或下游信道接收数据传输，并且用于通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。

6. 发明授权

US07447831B2 Memory systems for automated computing machinery 有权
标题翻译：自动计算机的存储系统
公开(公告)号：US07447831B2
公开(公告)日：2008-11-04
申请号：US11383989
申请日：2006-05-18
申请人： Daniel M. Dreps , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Daniel M. Dreps , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F13/14
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.
摘要翻译：公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。

7. 发明申请

US20070297397A1 Memory Systems for Automated Computing Machinery 失效
标题翻译：自动计算机存储系统
公开(公告)号：US20070297397A1
公开(公告)日：2007-12-27
申请号：US11426047
申请日：2006-06-23
申请人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
IPC分类号： H04L12/50
CPC分类号： G06F13/1684 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module, where memory module includes a memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, with the high speed memory bus connected to the memory hub device by a negligible electrical stub.
摘要翻译：公开了包括存储器控制器的存储器系统; 一个内存总线终端; 连接存储器控制器，存储器总线终端器和至少一个存储器模块的高速存储器总线，其中存储器模块包括存储器集线器设备，由存储器集线器设备服务的高速随机存取存储器，两个总线信号端口和在存储器模块上制造的高速存储器总线的一段，以便将总线信号端口和存储器集线器设备互连，高速存储器总线通过可忽略的电接头连接到存储器集线器装置。

8. 发明授权

US08327105B2 Providing frame start indication in a memory system having indeterminate read data latency 有权
标题翻译：在具有不确定的读数据延迟的存储器系统中提供帧起始指示
公开(公告)号：US08327105B2
公开(公告)日：2012-12-04
申请号：US13397819
申请日：2012-02-16
申请人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A memory system, having indeterminate read data latency, that includes a memory controller and one or more hub devices. The memory controller is configured for receiving data transfers via an upstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting a frame start indicator. The data frame includes an identification tag that is utilized by the memory controller to associate the data frame with a corresponding read instruction issued by the memory controller. The one or more hub devices are in communication with the memory controller in a cascade interconnect manner via the upstream channel and a downstream channel. Each hub device is configured for receiving the data transfers via the upstream channel or the downstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting the frame start indicator.
摘要翻译：具有不确定的读取数据延迟的存储器系统，其包括存储器控制器和一个或多个集线器设备。存储器控制器被配置为经由上游信道接收数据传输，并且通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。数据帧包括由存储器控制器用于将数据帧与由存储器控制器发出的相应读取指令相关联的识别标签。一个或多个集线器设备经由上游信道和下游信道以级联互连方式与存储器控制器通信。每个集线器设备被配置用于经由上游信道或下游信道接收数据传输，并且用于通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。

9. 发明申请

US20110199843A1 Strobe Offset in Bidirectional Memory Strobe Configurations 有权
标题翻译：双向内存频闪配置中的频闪偏移
公开(公告)号：US20110199843A1
公开(公告)日：2011-08-18
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译：一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

10. 发明申请

US20080215790A1 Memory systems for automated computing machinery 失效
标题翻译：自动计算机的存储系统
公开(公告)号：US20080215790A1
公开(公告)日：2008-09-04
申请号：US12102034
申请日：2008-04-14
申请人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
IPC分类号： G06F13/36
CPC分类号： G06F13/1684 , Y02D10/14
摘要： Design structures embodied in machine readable medium are provided. Embodiments of the design structure include a memory system comprising: a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module; and the at least one memory module, the memory module comprising at least one memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, the high speed memory bus connected to the memory hub device by a negligible electrical stub.
摘要翻译：提供体现在机器可读介质中的设计结构。设计结构的实施例包括存储器系统，包括：存储器控制器; 一个内存总线终端; 将存储器控制器，存储器总线终端器和至少一个存储器模块互连的高速存储器总线; 和所述至少一个存储器模块，所述存储器模块包括至少一个存储器集线器设备，由所述存储器集线器设备服务的高速随机存取存储器，两个总线信号端口以及在所述存储器模块上制造的所述高速存储器总线的段以便将总线信号端口和存储器集线器设备互连，高速存储器总线通过可忽略的电接头连接到存储器集线器设备。

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