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11. 发明授权

US07018868B1 Disposable hard mask for memory bitline scaling 有权
标题翻译：用于存储器位线缩放的一次性硬掩模
公开(公告)号：US07018868B1
公开(公告)日：2006-03-28
申请号：US10770245
申请日：2004-02-02
申请人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
发明人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
IPC分类号： H01L21/44
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和半导体器件的制造方法。半导体器件包括在半导体衬底中的掩埋位线。此外，掺杂区域形成在掩埋位线附近。与掩埋位线相邻的掺杂区域可以防止掩埋位线之间的漏电流。

12. 发明申请

US20050229125A1 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques 有权
标题翻译：使用光学规则检查进行集成电路器件设计和制造的屏幕分辨率增强技术的系统和方法
公开(公告)号：US20050229125A1
公开(公告)日：2005-10-13
申请号：US10816764
申请日：2004-04-02
申请人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
发明人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

13. 发明授权

US06855608B1 Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance 失效
标题翻译：制造平面结构电荷捕获具有矩形栅极的存储单元阵列并降低位线电阻的方法
公开(公告)号：US06855608B1
公开(公告)日：2005-02-15
申请号：US10463643
申请日：2003-06-17
申请人： Mark Ramsbey , Mark W. Randolph , Jean Yee-Mei Yang , Hiroyuki Kinoshita , Cyrus Tabery , Jeff P. Erhardt , Tazrien Kamal , Jaeyong Park , Emmanuil H. Lingunis
发明人： Mark Ramsbey , Mark W. Randolph , Jean Yee-Mei Yang , Hiroyuki Kinoshita , Cyrus Tabery , Jeff P. Erhardt , Tazrien Kamal , Jaeyong Park , Emmanuil H. Lingunis
IPC分类号： G11C16/04 , H01L21/336 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/0491 , H01L27/105 , H01L27/11573
摘要： A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls. The oxide is removed to expose the substrate between insulating spacers in the bit line regions and a conductor is fabricated thereon to enhance conductivity of each bit line.
摘要翻译：制造具有矩形栅极的平面架构电荷俘获介质存储单元阵列的方法包括在衬底的表面上制造多层电荷俘获电介质。与衬底相邻的层可以是氧化物。在电荷捕获电介质上沉积多晶硅层。在多晶硅层上施加字线掩模以在第一方向上屏蔽线性字线并且在其间露出沟槽区域，并且蚀刻沟槽以暴露沟槽区域中的电荷俘获电介质。将位线掩模施加在多晶硅层上以在垂直于第一方向的第二方向上屏蔽栅极，并在其间暴露位线区域，并蚀刻位线以暴露位线区域中的氧化物。植入位线，并在暴露的侧壁上制造绝缘间隔物。去除氧化物以在位线区域中的绝缘间隔物之间露出衬底，并且在其上制造导体以增强每个位线的导电性。

14. 发明申请

US20070209030A1 SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE DESIGN AND MANUFACTURE USING OPTICAL RULE CHECKING TO SCREEN RESOLUTION ENHANCEMENT TECHNIQUES 有权
标题翻译：使用光学规则检查分辨率增强技术的集成电路设备和制造的系统和方法
公开(公告)号：US20070209030A1
公开(公告)日：2007-09-06
申请号：US11741845
申请日：2007-04-30
申请人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
发明人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

15. 发明授权

US06987048B1 Memory device having silicided bitlines and method of forming the same 有权
标题翻译：具有硅化位线的存储器件及其形成方法
公开(公告)号：US06987048B1
公开(公告)日：2006-01-17
申请号：US10635781
申请日：2003-08-06
申请人： Ning Cheng , Hiroyuki Kinoshita , Jeff P. Erhardt , Mark T. Ramsbey , Cyrus Tabery , Jean Yee-Mei Yang
发明人： Ning Cheng , Hiroyuki Kinoshita , Jeff P. Erhardt , Mark T. Ramsbey , Cyrus Tabery , Jean Yee-Mei Yang
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11568 , Y10S438/954
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate, a bottom dielectric, a charge storing layer, and a top dielectric in a stacked gate configuration. Silicided buried bitlines, which function as a source and a drain, are formed within the substrate. The silicided bitlines have a reduced resistance, which greatly reduces the number of bitline contacts necessary in an array of memory devices.
摘要翻译：提供了存储器件和制造方法。存储器件包括半导体衬底，底部电介质，电荷存储层和堆叠栅极配置中的顶部电介质。用作源极和漏极的硅化掩埋位线形成在衬底内。硅化的位线具有降低的电阻，这大大减少了存储器件阵列中所需的位线接触的数量。

16. 发明申请

US20050221233A1 System and method for fabricating contact holes 有权
标题翻译：制造接触孔的系统和方法
公开(公告)号：US20050221233A1
公开(公告)日：2005-10-06
申请号：US10817193
申请日：2004-04-02
申请人： Anna Minvielle , Cyrus Tabery , Hung-eil Kim , Jongwook Kye
发明人： Anna Minvielle , Cyrus Tabery , Hung-eil Kim , Jongwook Kye
IPC分类号： G03F7/20 , G03F7/00
CPC分类号： G03F7/70425 , G03F7/70091 , G03F7/701 , G03F7/70125 , G03F7/70158
摘要： A method of forming a plurality of contact holes of varying pitch and density in a contact layer of an integrated circuit device is provided. The plurality of contact holes can include a plurality of regularly spaced contact holes having a first pitch along a first direction and a plurality of semi-isolated contact holes having a second pitch along a second direction. A double-dipole illumination source can transmit light energy through a mask having a pattern corresponding to a desired contact hole pattern. The double-dipole illumination source can include a first dipole aperture, which is oriented and optimized for patterning the regularly spaced contact holes, and a second dipole aperture, which is oriented substantially orthogonal to the first dipole aperture and optimized for patterning the plurality of semi-isolated contact holes. The contact layer can be etched using the patterned photoresist layer.
摘要翻译：提供了一种在集成电路器件的接触层中形成多个具有不同间距和密度的接触孔的方法。多个接触孔可以包括沿着第一方向具有第一间距的多个规则间隔的接触孔和沿第二方向具有第二间距的多个半隔离接触孔。双偶极照明源可以通过具有对应于期望的接触孔图案的图案的掩模传输光能。双偶极照明源可以包括第一偶极孔，其被定向和优化以用于图案化规则间隔的接触孔，以及第二偶极孔，其基本上垂直于第一偶极孔定向并且被优化用于图案化多个半隔离接触孔。可以使用图案化的光致抗蚀剂层来蚀刻接触层。

17. 发明授权

US06780708B1 METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY 有权
标题翻译：形成核心和外围门的方法，包括两个关键掩蔽步骤，以形成一个核心区域的硬掩模，其中包括在一个分辨率限制下无法达到的关键尺寸
公开(公告)号：US06780708B1
公开(公告)日：2004-08-24
申请号：US10382744
申请日：2003-03-05
申请人： Hiroyuki Kinoshita , Yu Sun , Basab Banerjee , Christopher M. Foster , John R. Behnke , Cyrus Tabery
发明人： Hiroyuki Kinoshita , Yu Sun , Basab Banerjee , Christopher M. Foster , John R. Behnke , Cyrus Tabery
IPC分类号： H01L218242
CPC分类号： H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
摘要翻译：一种用于形成半导体器件的方法，其包括在衬底上的层中具有可变节距和临界尺寸的线和间隔图案。衬底包括第一区域（例如芯区域）和第二区域（例如，周边区域）。第一区域中的第一子线和空间图案包括尺寸（A）的空间小于单独通过光刻工艺可实现的尺寸。此外，第二区域中的第二子线和空间图案包括至少一条线，其包括通过光刻可实现的第二临界尺寸（B）。该方法使用两个关键的掩模步骤来形成硬掩模，其在芯部区域中包括小于在光刻的分辨率极限下可实现的临界尺寸（A）。此外，该方法使用单个蚀刻步骤将硬掩模的图案转移到该层。

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