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11. 发明授权

US07095073B2 High K artificial lattices for capacitor applications to use in Cu or Al BEOL 有权
标题翻译：用于电容器应用的高K人造晶格用于Cu或Al BEOL
公开(公告)号：US07095073B2
公开(公告)日：2006-08-22
申请号：US10972551
申请日：2004-10-25
申请人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
发明人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
IPC分类号： H01L29/76
CPC分类号： H01L28/56 , H01L21/3141 , H01L21/3142 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L28/90
摘要： An improved and new process of fabricating high dielectric constant MIM capacitors. These high dielectric constant MIM capacitor met all of the stringent requirements needed for both for both RF and analog circuit applications. For the high dielectric constant MIM capacitor, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of layers either 4/4, 2/2, and 1/1 artificial layers. Hence thickness of the film can be easily controlled. Enhancement of dielectric constant is because of interface. Dielectric constants near 900 can be easily achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques is used for this type layer growth process.
摘要翻译：一种制造高介电常数MIM电容器的改进和新工艺。这些高介电常数MIM电容器满足RF和模拟电路应用两者所需的所有严格要求。对于高介电常数MIM电容器，金属在双镶嵌工艺中由铜电极组成。超级晶格的介电常数与总体厚度的关系由4/4，2/2和1/1人造层的层数控制。因此，可以容易地控制膜的厚度。介电常数的增强是由于界面。接近900的介电常数可以很容易地达到250埃厚的超晶格。 MBE，分子束外延或ALCVD，原子层CVD技术用于这种类型的层生长过程。

12. 发明授权

US06743291B2 Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth 有权
标题翻译：使用双选择性外延生长制造具有集成的超陡逆向双井的CMOS器件的方法
公开(公告)号：US06743291B2
公开(公告)日：2004-06-01
申请号：US10191850
申请日：2002-07-09
申请人： Chew Hoe Ang , Wenhe Lin , Jia Zhen Zheng
发明人： Chew Hoe Ang , Wenhe Lin , Jia Zhen Zheng
IPC分类号： C30B2522
CPC分类号： C30B29/06 , C30B25/20
摘要： A process of fabricating a CMOS device comprised with super-steep retrograde (SSR), twin well regions, has been developed. The process features the use of two, selective epitaxial growth (SEG), procedures, with the first SEG procedure resulting in the growth of bottom silicon shapes in the PMOS, as well as in the NMOS region of the CMOS device. After implantation of the ions needed for the twin well regions, into the bottom silicon shapes, a second SEG procedure is employed resulting in growth of top silicon shapes on the underlying, implanted bottom silicon shapes. An anneal procedure then distributes the implanted ions resulting in an SSR N well region in the composite silicon shape located in the PMOS region, and resulting in an SSR P well region in the composite silicon shape located in the NMOS region of the CMOS device.
摘要翻译：已经开发了制造具有超陡逆行（SSR）双阱区的CMOS器件的工艺。该方法的特征在于采用两种选择性外延生长（SEG）方法，其中第一种SEG方法导致PMOS中的底部硅形状以及CMOS器件的NMOS区域的生长。在将双阱区域所需的离子植入底部硅形状之后，采用第二种SEG方法，导致底层硅底部形状的顶部硅形状的增长。退火程序然后分布注入的离子，得到位于PMOS区域的复合硅形状中的SSR N阱区，并且导致位于CMOS器件的NMOS区域中的复合硅形状中的SSR P阱区。

13. 发明授权

US06734082B2 Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape 有权
标题翻译：形成浅沟槽隔离结构的方法，其特征在于位于浅沟槽形状的表面上的一组绝缘体衬垫层
公开(公告)号：US06734082B2
公开(公告)日：2004-05-11
申请号：US10213173
申请日：2002-08-06
申请人： Jia Zhen Zheng , Soh Yun Siah , Chew Hoe Ang
发明人： Jia Zhen Zheng , Soh Yun Siah , Chew Hoe Ang
IPC分类号： H01L2146
CPC分类号： H01L21/76232
摘要： A process for forming a shallow trench isolation (STI), structure in a semiconductor substrate, featuring a group of insulator liner layers located on the surfaces of the shallow trench shape used to accommodate the STI structure, has been developed. After defining a shallow trench shape featuring rounded corners, a group of thin insulator liner layers, each comprised of either silicon oxide or silicon nitride, is deposited on the exposed surfaces of the shallow trench shape via atomic layer depositing (ALD), procedures. A high density plasma procedure is used for deposition of silicon oxide, filling the shallow trench shape which is lined with the group of thin insulator liner layers. The silicon nitride component of the insulator liner layers, prevents diffusion or segregation of P type dopants from an adjacent P well region to the silicon oxide of the STI structure.
摘要翻译：已经开发了用于形成半导体衬底中的浅沟槽隔离（STI）结构的方法，其特征在于位于用于容纳STI结构的浅沟槽形状的表面上的一组绝缘体衬垫层。在定义了具有圆角的浅沟槽形状之后，通过原子层沉积（ALD）方法将沉积在浅沟槽形状的暴露表面上的一组薄的绝缘体衬垫层（每个都由氧化硅或氮化硅组成）沉积在一起。使用高密度等离子体方法沉积氧化硅，填充衬有薄绝缘体衬层层的浅沟槽形状。绝缘体衬垫层的氮化硅组分防止P型掺杂剂从相邻P阱区扩散或分离到STI结构的氧化硅上。

14. 发明授权

US07176094B2 Ultra-thin gate oxide through post decoupled plasma nitridation anneal 有权
标题翻译：超薄栅氧化层通过后解耦等离子体氮化退火
公开(公告)号：US07176094B2
公开(公告)日：2007-02-13
申请号：US10091983
申请日：2002-03-06
申请人： Dong Zhong , Yun Ling Tan , Chew Hoe Ang , Jia Zhen Zheng
发明人： Dong Zhong , Yun Ling Tan , Chew Hoe Ang , Jia Zhen Zheng
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/0214 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28202 , H01L21/3105 , H01L21/3144 , H01L21/324 , H01L29/518
摘要： DPN (decoupled plasma nitridation) is used to improve robustness of ultra thin gate oxides. Conventionally, this is followed by an anneal in pure helium to remove structural defects in the oxide. However, annealing under these conditions has been found to cause a deterioration of the electrical performance of devices. This problem has been overcome by annealing, in a 1:4 oxygen-nitrogen mixture (1,050° C. at about 10 torr) instead of in helium or nitrogen oxide. This results in a gate oxide that is resistant to boron contamination without suffering any loss in its electrical properties.
摘要翻译： DPN（去耦等离子体氮化）用于提高超薄栅极氧化物的鲁棒性。通常，随后在纯氦中进行退火以去除氧化物中的结构缺陷。然而，已经发现在这些条件下的退火会导致器件的电性能的劣化。在1：4的氧 - 氮混合物（约10托的1050℃）中代替在氦或氮氧化物中退火，已经克服了这个问题。这导致对硼污染具有耐受性的栅极氧化物，而不会在其电性能方面遭受任何损失。

15. 发明授权

US06670248B1 Triple gate oxide process with high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的三栅极氧化物工艺
公开(公告)号：US06670248B1
公开(公告)日：2003-12-30
申请号：US10213610
申请日：2002-08-07
申请人： Chew Hoe Ang , Wenhe Lin , Jia Zhen Zheng
发明人： Chew Hoe Ang , Wenhe Lin , Jia Zhen Zheng
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/823462 , H01L21/823857 , H01L29/513 , H01L29/517
摘要： A method for forming, on a semiconductor substrate, a dielectric layer having a variable thickness and composition. The dielectric layer so formed can be used to form electronic devices such as MOSFETS and CMOSFETS that require gate dielectrics of different thicknesses. On a silicon substrate in accord with the preferred embodiment, the method requires the formation of three regions, two with SiO2 layers of different thicknesses and a third region of substrate with no oxide. A final thin layer of high-k dielectric is formed covering the three regions, so that the region with no oxide has the thinnest dielectric layer of only high-k material and the other two regions have the high-k dielectric over SiO2 layers of different thickness. A final layer of gate electrode material can be formed and patterned to form the required device structure.
摘要翻译：一种在半导体衬底上形成具有可变厚度和组成的介电层的方法。如此形成的电介质层可用于形成需要不同厚度栅极电介质的电子器件，如MOSFET和CMOSFET。在根据优选实施例的硅衬底上，该方法需要形成三个区域，两个具有不同厚度的SiO 2层和没有氧化物的衬底的第三区域。形成了覆盖三个区域的最终的高k电介质的薄层，使得没有氧化物的区域具有仅最高k材料的最薄的电介质层，而另外两个区域具有不同SiO 2层上的高k电介质厚度。可以形成和图案化最终的栅电极材料层以形成所需的器件结构。

16. 发明授权

US06709912B1 Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization 失效
标题翻译：具有不同Ge浓度的双Si-Ge多晶硅栅极用于CMOS器件优化
公开(公告)号：US06709912B1
公开(公告)日：2004-03-23
申请号：US10266425
申请日：2002-10-08
申请人： Chew-Hoe Ang , Jeffrey Chee Wei-Lun , Wenhe Lin , Jia Zhen Zheng
发明人： Chew-Hoe Ang , Jeffrey Chee Wei-Lun , Wenhe Lin , Jia Zhen Zheng
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , Y10S438/933
摘要： A method for forming a dual Si—Ge poly-gates having different Ge concentrations is described. An NMOS active area and a PMOS active area are provided on a semiconductor substrate separated by an isolation region. A gate oxide layer is grown overlying the semiconductor substrate in each of the active areas. A polycrystalline silicon-germanium (Si—Ge) layer is deposited overlying the gate oxide layer wherein the polycrystalline Si—Ge layer has a first Ge concentration. The NMOS active area is blocked while the PMOS active area is exposed. Successive cycles of Ge plasma doping and laser annealing into the PMOS active area are performed to achieve a second Ge concentration higher than the first Ge concentration. The polycrystalline Si—Ge layer is patterned to form a gate in each of the active areas wherein the gate in the PMOS active area has a higher Ge concentration than the gate in the NMOS active area to complete formation of dual Si—Ge polysilicon gates with different Ge concentrations in the fabrication of an integrated circuit device.
摘要翻译：描述了形成具有不同Ge浓度的双Si-Ge多栅极的方法。在由隔离区隔开的半导体衬底上提供NMOS有源区和PMOS有源区。生长在每个有源区域中的半导体衬底上的栅氧化层。沉积在多晶Si-Ge层具有第一Ge浓度的栅极氧化物层上的多晶硅 - 锗（Si-Ge）层。当PMOS有源区域暴露时，NMOS有源区域被阻塞。进行Ge等离子体掺杂和激光退火到PMOS有源区的连续循环以实现高于第一Ge浓度的第二Ge浓度。多晶Si-Ge层被图案化以在每个有源区域中形成栅极，其中PMOS有源区中的栅极具有比NMOS有源区域中的栅极更高的Ge浓度，以完成双Si-Ge多晶硅栅极的形成，在集成电路器件的制造中不同的Ge浓度。

17. 发明授权

US06403425B1 Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide 有权
标题翻译：双栅极氧化物工艺，由于厚栅氧化物而导致薄栅沟道注入分布的热分布降低
公开(公告)号：US06403425B1
公开(公告)日：2002-06-11
申请号：US09995191
申请日：2001-11-27
申请人： Chew-Hoe Ang , Wenhe Lin , Jia Zhen Zheng
发明人： Chew-Hoe Ang , Wenhe Lin , Jia Zhen Zheng
IPC分类号： H01L218234
CPC分类号： H01L21/823857
摘要： A new method is provided for the creation of layers of gate oxide of different thicknesses. A substrate is provided, the surface of the substrate is divided into a first surface region over which a thick layer of gate oxide has to be created and a second surface region over which a thin layer of gate oxide is to be created. Thick gate-oxide implants are performed into the surface of the substrate. A thick layer of gate oxide is created over the surface of the substrate, the thick layer of gate oxide is successively patterned for thin gate-oxide implants, comprising thin gate-oxide n-well/p-well, threshold, punchthrough implants, into the second surface region of the substrate. The thick layer of gate oxide is removed from the second surface region of the substrate. The (now contaminated) top layer of the thick layer of gate oxide is removed, a thin layer of gate oxide is grown over the second surface region of the substrate.
摘要翻译：提供了一种新的形成不同厚度栅极氧化层的方法。提供了一种衬底，衬底的表面被分成第一表面区域，在该第一表面区域上必须产生一个厚的栅极氧化层，另一个表面区域将形成一薄层的栅极氧化物。将厚栅氧化物植入物进行到衬底的表面。在衬底的表面上形成厚层栅极氧化物，栅极氧化物的厚层依次构图用于薄栅极氧化物植入物，其包括薄的栅极氧化物n阱/ p阱，阈值穿透植入物衬底的第二表面区域。栅极氧化物的厚层从衬底的第二表面区域去除。去除栅极氧化物的厚层的（现在被污染的）顶层，在衬底的第二表面区域上生长薄层的栅极氧化物。

18. 发明授权

US06544824B1 Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel 失效
标题翻译：通过首先形成栅/间隔堆叠形成垂直晶体管的方法，然后使用选择性外延形成源极，漏极和沟道
公开(公告)号：US06544824B1
公开(公告)日：2003-04-08
申请号：US10038390
申请日：2002-01-03
申请人： Yelehanka Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Lee Yong Meng , Ying Keung
发明人： Yelehanka Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Lee Yong Meng , Ying Keung
IPC分类号： H01L2100
CPC分类号： H01L29/66666
摘要： A method of manufacturing a vertical transistor. A doped region is formed in a substrate. We form sequentially on the substrate: a first spacer dielectric layer, a first gate electrode, a second spacer dielectric layer, a second gate electrode and a third spacer dielectric layer. A trench is formed through the first spacer dielectric layer, the first gate electrode, the second spacer dielectric layer, the second gate electrode and the third spacer dielectric layer. The trench has sidewalls. A gate dielectric layer is formed over the sidewalls of the trench. We form sequentially, in the trench: a first doped layer, a first channel layer, a second doped layer, a third doped layer, a second channel layer, and a fourth doped layer. A cap layer is formed over the structure. Contacts are preferably formed to the doped region, doped layers and gate electrodes.
摘要翻译：一种垂直晶体管的制造方法。在衬底中形成掺杂区域。我们在衬底上依次形成：第一间隔电介质层，第一栅电极，第二间隔电介质层，第二栅电极和第三间隔电介质层。通过第一间隔电介质层，第一栅电极，第二间隔电介质层，第二栅电极和第三间隔电介质层形成沟槽。沟槽有侧壁。栅极电介质层形成在沟槽的侧壁上。我们在沟槽中依次形成：第一掺杂层，第一沟道层，第二掺杂层，第三掺杂层，第二沟道层和第四掺杂层。在该结构上形成盖层。触点优选地形成于掺杂区域，掺杂层和栅电极。

19. 发明授权

US06468877B1 Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner 有权
标题翻译：通过使用一次性间隔件/衬垫在栅电极的边缘下形成气隙的方法
公开(公告)号：US06468877B1
公开(公告)日：2002-10-22
申请号：US09907651
申请日：2001-07-19
申请人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
发明人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
IPC分类号： H01L2176
CPC分类号： H01L21/7682 , H01L21/764 , H01L21/823468 , H01L29/4983
摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.
摘要翻译：一种制造半导体器件的气隙间隔物的方法，包括以下步骤。提供具有至少一对限定有源区域的STI的半导体衬底。在有源区内的基板上形成栅电极。栅电极具有底层栅介电层。在该结构上形成衬里氧化物层，覆盖栅极电介质层的侧壁，栅电极以及栅电极的顶表面。在衬垫氧化物层上形成衬里氮化物层。在结构上形成厚的氧化物层。厚氧化物，衬里氮化物和衬里氧化物层与栅电极的顶表面平坦化，并且在栅电极的任一侧暴露衬里氧化物层。用一部分衬垫氧化物层和栅电介质层的一部分在栅电极下方去除平坦化的厚氧化物层，以在栅电极的任一侧上形成横截面倒置的T形开口。在该结构上形成至少与栅电极一样厚的栅极间隔氧化物层，其中栅极间隔物氧化物层从顶部向下部分地填充倒置的T形开口，并且其中气隙间隔物邻近倒置的底部形成 T形开口。蚀刻栅间隔氧化物，衬里氮化物和衬里氧化物层以在栅电极附近形成栅极间隔。栅极间隔物具有下面的蚀刻衬里氮化物层和衬里氧化物层。

20. 发明授权

US06455377B1 Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) 失效
标题翻译：通过SiGe或多量子阱（MQW）的选择性沉积形成非常高迁移率的垂直沟道晶体管的方法
公开(公告)号：US06455377B1
公开(公告)日：2002-09-24
申请号：US09765040
申请日：2001-01-19
申请人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
发明人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/1054 , H01L29/66916 , H01L29/7827 , H01L29/802
摘要： A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.
摘要翻译：一种制造垂直沟道晶体管的方法，包括以下步骤。提供具有上表面的半导体衬底。在半导体衬底上形成高掺杂N型下部外延硅层。在下部外延硅层上形成低掺杂P型中间外延硅层。在中间外延硅层上形成高掺杂N型上部外延硅层。蚀刻下部，中间和上部外延硅层以形成由隔离沟槽限定的外延层堆叠。在隔离槽内形成氧化物。氧化物被蚀刻以在一个隔离沟槽内形成栅极沟槽，暴露外延层堆叠面向栅极沟槽的侧壁。在暴露的外延层堆叠侧壁上形成多量子阱或染色层超晶格。在多量子阱或染色层超晶格上并在栅极沟槽内形成栅介质层。栅极导体层形成在栅极电介质层上，填充栅极沟槽。

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