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1. 发明授权

US06664156B1 Method for forming L-shaped spacers with precise width control 有权
标题翻译：用于形成具有精确宽度控制的L形间隔件的方法
公开(公告)号：US06664156B1
公开(公告)日：2003-12-16
申请号：US10209573
申请日：2002-07-31
申请人： Chew Hoe Ang , Eng Hua Lim , Wenhe Lin , Jia Zhen Zheng
发明人： Chew Hoe Ang , Eng Hua Lim , Wenhe Lin , Jia Zhen Zheng
IPC分类号： H01L21311
CPC分类号： H01L29/6653 , H01L29/4983 , H01L29/6656 , H01L29/6659
摘要： A method of fabrication of L-shaped spacers in a semiconductor device. A gate structure is provided over a substrate. We form a first dielectric layer over the gate dielectric layer and the substrate. Next, a second dielectric layer is formed over the first dielectric layer. Then, we form a third dielectric layer over the second dielectric layer. The third dielectric layer is anisotropically etched to form a disposable spacer on the second dielectric layer. The second dielectric layer and the first dielectric layer are anisotropically etched using the disposable spacer as a mask to form a top and a bottom L-shaped spacer. The disposable spacer is removed. In preferred embodiments, the first, second and third dielectric layers are formed by atomic layer deposition (ALD) or ALCVD processes.
摘要翻译：一种在半导体器件中制造L形间隔物的方法。栅极结构设置在衬底上。我们在栅极电介质层和衬底上形成第一电介质层。接下来，在第一电介质层上形成第二电介质层。然后，在第二电介质层上形成第三电介质层。第三介电层被各向异性蚀刻以在第二介电层上形成一次性间隔物。使用一次性间隔件作为掩模对第二介电层和第一介电层进行各向异性蚀刻，以形成顶部和底部的L形间隔件。去除一次性间隔物。在优选实施例中，第一，第二和第三电介质层通过原子层沉积（ALD）或ALCVD工艺形成。

2. 发明授权

US06743291B2 Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth 有权
标题翻译：使用双选择性外延生长制造具有集成的超陡逆向双井的CMOS器件的方法
公开(公告)号：US06743291B2
公开(公告)日：2004-06-01
申请号：US10191850
申请日：2002-07-09
申请人： Chew Hoe Ang , Wenhe Lin , Jia Zhen Zheng
发明人： Chew Hoe Ang , Wenhe Lin , Jia Zhen Zheng
IPC分类号： C30B2522
CPC分类号： C30B29/06 , C30B25/20
摘要： A process of fabricating a CMOS device comprised with super-steep retrograde (SSR), twin well regions, has been developed. The process features the use of two, selective epitaxial growth (SEG), procedures, with the first SEG procedure resulting in the growth of bottom silicon shapes in the PMOS, as well as in the NMOS region of the CMOS device. After implantation of the ions needed for the twin well regions, into the bottom silicon shapes, a second SEG procedure is employed resulting in growth of top silicon shapes on the underlying, implanted bottom silicon shapes. An anneal procedure then distributes the implanted ions resulting in an SSR N well region in the composite silicon shape located in the PMOS region, and resulting in an SSR P well region in the composite silicon shape located in the NMOS region of the CMOS device.
摘要翻译：已经开发了制造具有超陡逆行（SSR）双阱区的CMOS器件的工艺。该方法的特征在于采用两种选择性外延生长（SEG）方法，其中第一种SEG方法导致PMOS中的底部硅形状以及CMOS器件的NMOS区域的生长。在将双阱区域所需的离子植入底部硅形状之后，采用第二种SEG方法，导致底层硅底部形状的顶部硅形状的增长。退火程序然后分布注入的离子，得到位于PMOS区域的复合硅形状中的SSR N阱区，并且导致位于CMOS器件的NMOS区域中的复合硅形状中的SSR P阱区。

3. 发明授权

US06670248B1 Triple gate oxide process with high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的三栅极氧化物工艺
公开(公告)号：US06670248B1
公开(公告)日：2003-12-30
申请号：US10213610
申请日：2002-08-07
申请人： Chew Hoe Ang , Wenhe Lin , Jia Zhen Zheng
发明人： Chew Hoe Ang , Wenhe Lin , Jia Zhen Zheng
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/823462 , H01L21/823857 , H01L29/513 , H01L29/517
摘要： A method for forming, on a semiconductor substrate, a dielectric layer having a variable thickness and composition. The dielectric layer so formed can be used to form electronic devices such as MOSFETS and CMOSFETS that require gate dielectrics of different thicknesses. On a silicon substrate in accord with the preferred embodiment, the method requires the formation of three regions, two with SiO2 layers of different thicknesses and a third region of substrate with no oxide. A final thin layer of high-k dielectric is formed covering the three regions, so that the region with no oxide has the thinnest dielectric layer of only high-k material and the other two regions have the high-k dielectric over SiO2 layers of different thickness. A final layer of gate electrode material can be formed and patterned to form the required device structure.
摘要翻译：一种在半导体衬底上形成具有可变厚度和组成的介电层的方法。如此形成的电介质层可用于形成需要不同厚度栅极电介质的电子器件，如MOSFET和CMOSFET。在根据优选实施例的硅衬底上，该方法需要形成三个区域，两个具有不同厚度的SiO 2层和没有氧化物的衬底的第三区域。形成了覆盖三个区域的最终的高k电介质的薄层，使得没有氧化物的区域具有仅最高k材料的最薄的电介质层，而另外两个区域具有不同SiO 2层上的高k电介质厚度。可以形成和图案化最终的栅电极材料层以形成所需的器件结构。

4. 发明授权

US06830971B2 High K artificial lattices for capacitor applications to use in CU or AL BEOL 有权
标题翻译：用于电容器应用的高K人造晶格用于CU或AL BEOL
公开(公告)号：US06830971B2
公开(公告)日：2004-12-14
申请号：US10286627
申请日：2002-11-02
申请人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
发明人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
IPC分类号： H01L218242
CPC分类号： H01L28/56 , H01L21/3141 , H01L21/3142 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L28/90
摘要： A process of fabricating high dielectric constant MIM capacitors. The high dielectric constant MIM capacitors are for both RF and analog circuit applications. For the high dielectric constant MIM capacitors, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of artificial layers. Dielectric constants near 900 can be achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques are employed for the layer growth processes.
摘要翻译：制造高介电常数MIM电容器的工艺。高介电常数MIM电容器适用于RF和模拟电路应用。对于高介电常数MIM电容器，金属由双重镶嵌工艺中的铜电极组成。超级晶格的介电常数与总厚度的关系由人造层的数量来控制。接近900的介电常数可以达到250埃厚的超晶格。 MBE，分子束外延或ALCVD，原子层CVD技术用于层生长过程。

5. 发明授权

US06586314B1 Method of forming shallow trench isolation regions with improved corner rounding 失效
标题翻译：形成浅沟槽隔离区域的方法具有改进的拐角圆角
公开(公告)号：US06586314B1
公开(公告)日：2003-07-01
申请号：US10266952
申请日：2002-10-08
申请人： Soh Yun Siah , Liang Choo Hsia , Jia Zhen Zheng , Chew Hoe Ang
发明人： Soh Yun Siah , Liang Choo Hsia , Jia Zhen Zheng , Chew Hoe Ang
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A method of forming a shallow trench isolation (STI), region in a semiconductor substrate featuring a process sequence that results in desired rounded corners for the sides of active device regions located butting the STI region, has been developed. The process sequence features formation of, followed by removal of, a silicon dioxide layer which was thermally grown in a top portion of the semiconductor substrate, wherein the top portion of semiconductor was subjected to an ion implantation procedure prior to the oxidation procedure. The above process sequence results in a recessed portion of semiconductor located adjacent to unoxidized portions of semiconductor which underlay an oxidation resistant shape, and feature rounded corners. Insulator spacers are then formed on the sides of the oxidation resistant shape, overlying and protecting the rounded comers of subsequent active device regions from a dry etch procedure used to selectively define a shallow trench shape in the exposed semiconductor region. Insulator filling and planarization procedures result in the formation of an STI region, located adjacent to active device regions which feature the desired rounded corners.
摘要翻译：已经开发了在半导体衬底中形成浅沟槽隔离（STI）区域的方法，该半导体衬底的特征在于产生针对STI区域的有源器件区域的侧面的期望的圆角的工艺序列。处理顺序特征在于形成，随后除去在半导体衬底的顶部热生长的二氧化硅层，其中半导体的顶部在氧化过程之前进行离子注入工艺。上述处理顺序导致位于半导体的未氧化部分附近的半导体的凹陷部分，其具有抗氧化的形状，并且具有圆角。然后在耐氧化形状的侧面上形成绝缘体间隔物，覆盖并保护随后的有源器件区域的圆角从用于在暴露的半导体区域中选择性地限定浅沟槽形状的干蚀刻工艺。绝缘体填充和平坦化程序导致STI区域的形成，其位于具有所需圆角的有源器件区域附近。

6. 发明授权

US07095073B2 High K artificial lattices for capacitor applications to use in Cu or Al BEOL 有权
标题翻译：用于电容器应用的高K人造晶格用于Cu或Al BEOL
公开(公告)号：US07095073B2
公开(公告)日：2006-08-22
申请号：US10972551
申请日：2004-10-25
申请人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
发明人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
IPC分类号： H01L29/76
CPC分类号： H01L28/56 , H01L21/3141 , H01L21/3142 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L28/90
摘要： An improved and new process of fabricating high dielectric constant MIM capacitors. These high dielectric constant MIM capacitor met all of the stringent requirements needed for both for both RF and analog circuit applications. For the high dielectric constant MIM capacitor, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of layers either 4/4, 2/2, and 1/1 artificial layers. Hence thickness of the film can be easily controlled. Enhancement of dielectric constant is because of interface. Dielectric constants near 900 can be easily achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques is used for this type layer growth process.
摘要翻译：一种制造高介电常数MIM电容器的改进和新工艺。这些高介电常数MIM电容器满足RF和模拟电路应用两者所需的所有严格要求。对于高介电常数MIM电容器，金属在双镶嵌工艺中由铜电极组成。超级晶格的介电常数与总体厚度的关系由4/4，2/2和1/1人造层的层数控制。因此，可以容易地控制膜的厚度。介电常数的增强是由于界面。接近900的介电常数可以很容易地达到250埃厚的超晶格。 MBE，分子束外延或ALCVD，原子层CVD技术用于这种类型的层生长过程。

7. 发明授权

US06734082B2 Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape 有权
标题翻译：形成浅沟槽隔离结构的方法，其特征在于位于浅沟槽形状的表面上的一组绝缘体衬垫层
公开(公告)号：US06734082B2
公开(公告)日：2004-05-11
申请号：US10213173
申请日：2002-08-06
申请人： Jia Zhen Zheng , Soh Yun Siah , Chew Hoe Ang
发明人： Jia Zhen Zheng , Soh Yun Siah , Chew Hoe Ang
IPC分类号： H01L2146
CPC分类号： H01L21/76232
摘要： A process for forming a shallow trench isolation (STI), structure in a semiconductor substrate, featuring a group of insulator liner layers located on the surfaces of the shallow trench shape used to accommodate the STI structure, has been developed. After defining a shallow trench shape featuring rounded corners, a group of thin insulator liner layers, each comprised of either silicon oxide or silicon nitride, is deposited on the exposed surfaces of the shallow trench shape via atomic layer depositing (ALD), procedures. A high density plasma procedure is used for deposition of silicon oxide, filling the shallow trench shape which is lined with the group of thin insulator liner layers. The silicon nitride component of the insulator liner layers, prevents diffusion or segregation of P type dopants from an adjacent P well region to the silicon oxide of the STI structure.
摘要翻译：已经开发了用于形成半导体衬底中的浅沟槽隔离（STI）结构的方法，其特征在于位于用于容纳STI结构的浅沟槽形状的表面上的一组绝缘体衬垫层。在定义了具有圆角的浅沟槽形状之后，通过原子层沉积（ALD）方法将沉积在浅沟槽形状的暴露表面上的一组薄的绝缘体衬垫层（每个都由氧化硅或氮化硅组成）沉积在一起。使用高密度等离子体方法沉积氧化硅，填充衬有薄绝缘体衬层层的浅沟槽形状。绝缘体衬垫层的氮化硅组分防止P型掺杂剂从相邻P阱区扩散或分离到STI结构的氧化硅上。

8. 发明授权

US07176094B2 Ultra-thin gate oxide through post decoupled plasma nitridation anneal 有权
标题翻译：超薄栅氧化层通过后解耦等离子体氮化退火
公开(公告)号：US07176094B2
公开(公告)日：2007-02-13
申请号：US10091983
申请日：2002-03-06
申请人： Dong Zhong , Yun Ling Tan , Chew Hoe Ang , Jia Zhen Zheng
发明人： Dong Zhong , Yun Ling Tan , Chew Hoe Ang , Jia Zhen Zheng
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/0214 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28202 , H01L21/3105 , H01L21/3144 , H01L21/324 , H01L29/518
摘要： DPN (decoupled plasma nitridation) is used to improve robustness of ultra thin gate oxides. Conventionally, this is followed by an anneal in pure helium to remove structural defects in the oxide. However, annealing under these conditions has been found to cause a deterioration of the electrical performance of devices. This problem has been overcome by annealing, in a 1:4 oxygen-nitrogen mixture (1,050° C. at about 10 torr) instead of in helium or nitrogen oxide. This results in a gate oxide that is resistant to boron contamination without suffering any loss in its electrical properties.
摘要翻译： DPN（去耦等离子体氮化）用于提高超薄栅极氧化物的鲁棒性。通常，随后在纯氦中进行退火以去除氧化物中的结构缺陷。然而，已经发现在这些条件下的退火会导致器件的电性能的劣化。在1：4的氧 - 氮混合物（约10托的1050℃）中代替在氦或氮氧化物中退火，已经克服了这个问题。这导致对硼污染具有耐受性的栅极氧化物，而不会在其电性能方面遭受任何损失。

9. 发明授权

US06664153B2 Method to fabricate a single gate with dual work-functions 失效
标题翻译：制造具有双功能功能的单门的方法
公开(公告)号：US06664153B2
公开(公告)日：2003-12-16
申请号：US10072099
申请日：2002-02-08
申请人： Chew Hoe Ang , Eng Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
发明人： Chew Hoe Ang , Eng Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
IPC分类号： H01L21336
CPC分类号： H01L29/4983 , H01L21/28035
摘要： A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.
摘要翻译：描述了一种形成具有双功能功能的单门的方法。在基板上形成覆盖栅介质层的栅电极。栅电极的侧壁被选择性掺杂，由此掺杂侧壁具有第一功函数，并且由此未掺杂的栅电极的中心部分具有第二功函数，以在制造中完成形成具有多个功函数的单个栅极的集成电路。

10. 发明授权

US06429109B1 Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate 有权
标题翻译：通过在氧化物和栅极之间使用牺牲金属来形成高k电介质和硅化物以减少多余的方法
公开(公告)号：US06429109B1
公开(公告)日：2002-08-06
申请号：US10017953
申请日：2001-12-14
申请人： Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen , Chew Hoe Ang , Eng Hua Lim , Randall Cha
发明人： Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen , Chew Hoe Ang , Eng Hua Lim , Randall Cha
IPC分类号： H01L214763
CPC分类号： H01L21/28194 , H01L21/28097 , H01L21/28176 , H01L21/28238 , H01L29/513 , H01L29/517
摘要： A method of forming a gate comprising the following steps. A substrate is provided. A pre-gate structure is formed over the substrate. The pregate structure includes a sacrificial metal layer between an upper gate conductor layer and a lower gate dielectric layer. The pre-gate structure is annealed to form the gate. The gate comprising: an upper silicide layer formed from a portion of the sacrificial metal layer and a portion of the upper gate conductor layer from the anneal; and a lower metal oxide layer formed from a portion of the gate dielectric layer and a portion of the sacrificial metal layer from the anneal.
摘要翻译：一种形成浇口的方法，包括以下步骤。提供基板。在衬底上形成预栅极结构。预栅结构包括在上栅极导体层和下栅极介电层之间的牺牲金属层。预栅结构退火形成栅极。该栅极包括：由牺牲金属层的一部分形成的上硅化物层和来自退火的上部栅极导体层的一部分; 以及由栅极电介质层的一部分和来自退火的牺牲金属层的一部分形成的下部金属氧化物层。

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