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11. 发明申请

US20110227132A1 FIELD-EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管
公开(公告)号：US20110227132A1
公开(公告)日：2011-09-22
申请号：US13118945
申请日：2011-05-31
申请人： Yoshiharu ANDA , Hidetoshi ISHIDA , Tetsuzo UEDA
发明人： Yoshiharu ANDA , Hidetoshi ISHIDA , Tetsuzo UEDA
IPC分类号： H01L29/205
CPC分类号： H01L29/42316 , H01L29/2003 , H01L29/4236 , H01L29/7787
摘要： The present invention has as an object to provide a FET having low on-resistance. The FET according to the present invention includes: first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a higher band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and having a higher band gap energy than the third nitride semiconductor layer. A channel is formed in a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer.
摘要翻译：本发明的目的是提供一种具有低导通电阻的FET。根据本发明的FET包括：第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更高的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上的第三氮化物半导体层; 形成在所述第三氮化物半导体层上并且具有比所述第三氮化物半导体层更高的带隙能量的第四氮化物半导体层。在第一氮化物半导体层和第二氮化物半导体层之间的异质结界面形成沟道。

12. 发明申请

US20080251837A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080251837A1
公开(公告)日：2008-10-16
申请号：US12054800
申请日：2008-03-25
申请人： Yoshiaki KATO , Yoshiharu ANDA , Akihiko NISHIO
发明人： Yoshiaki KATO , Yoshiharu ANDA , Akihiko NISHIO
IPC分类号： H01L21/04 , H01L49/00
CPC分类号： H01L29/7783 , H01L21/8252 , H01L27/0605 , H01L27/0883
摘要： A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer.
摘要翻译：包括E-FET和D-FET两者的半导体器件，并且可以有助于控制E-FET中的Vth，并抑制Vf的降低，并且提供其制造方法。在同一半导体衬底上包括E-FET和D-FET的半导体器件包括：用于调节E-FET的阈值的第一阈值调整层; 形成在第一阈值调整层上的第一蚀刻停止层; 所述第二阈值调整层形成在所述第一蚀刻停止层上，用于调节所述D-FET的阈值; 形成在所述第二阈值调整层上的第二蚀刻停止层; 穿过与第一阈值调整层接触的第一蚀刻停止层，第二阈值调节层和第二蚀刻阻挡层的第一栅电极; 并且所述第二栅电极贯穿与所述第二阈值调整层接触的所述第二蚀刻停止层。

13. 发明申请

US20060076585A1 Semiconductor resistor and method for manufacturing the same 审中-公开
标题翻译：半导体电阻及其制造方法
公开(公告)号：US20060076585A1
公开(公告)日：2006-04-13
申请号：US11234172
申请日：2005-09-26
申请人： Yoshiaki Kato , Yoshiharu Anda , Akiyoshi Tamura
发明人： Yoshiaki Kato , Yoshiharu Anda , Akiyoshi Tamura
IPC分类号： H01L31/112
CPC分类号： H01L27/0605 , H01L27/0629
摘要： An object of the present invention is to provide a semiconductor resistor that allows improvement in saturation voltage characteristics and a method for manufacturing the same. The semiconductor resistor of the present invention is formed on the substrate on which a GaAs FET is formed. The GaAs FET includes: a channel layer; a Schottky layer formed on the channel layer and made of undoped InGaP; and a contact layer formed on the Schottky layer. The semiconductor resistor includes: a contact layer including a part of the contact layer isolated from the GaAs FET; an active region including a part of the Schottky layer and a part of the channel layer, both of which are isolated from the GaAs FET; and two ohmic electrodes formed on the contact layer, and the Schottky layer isolated from the GaAs FET is exposed in an area between the two ohmic electrodes.
摘要翻译：本发明的一个目的是提供一种允许提高饱和电压特性的半导体电阻器及其制造方法。本发明的半导体电阻器形成在其上形成有GaAs FET的基板上。 GaAs FET包括：沟道层; 形成在沟道层上并由未掺杂的InGaP制成的肖特基层; 以及形成在肖特基层上的接触层。半导体电阻器包括：接触层，其包括与GaAs FET隔离的部分接触层; 包括肖特基层的一部分和沟道层的一部分的有源区域，两者都与GaAs FET隔离; 并且形成在接触层上的两个欧姆电极，并且从GaAs FET隔离的肖特基层暴露在两个欧姆电极之间的区域中。

14. 发明申请

US20050121695A1 Semiconductor device with Schottky electrode including lanthanum and boron, and manufacturing method thereof 有权
标题翻译：含有镧和硼的肖特基电极的半导体器件及其制造方法
公开(公告)号：US20050121695A1
公开(公告)日：2005-06-09
申请号：US11032164
申请日：2005-01-11
申请人： Yoshiharu Anda , Akiyoshi Tamura
发明人： Yoshiharu Anda , Akiyoshi Tamura
IPC分类号： H01L21/28 , H01L21/335 , H01L21/338 , H01L29/423 , H01L29/47 , H01L29/778 , H01L29/812 , H01L29/872 , H01L31/072 , H01L29/739
CPC分类号： H01L29/66462 , H01L29/475 , H01L29/7784
摘要： A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324, a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 composed of an undoped In0.48Ga0.52P material, and an n+-type GaAs cap layer 328. A gate electrode 330 is formed on the Schottky layer 327, and is composed of LaB6 and has a Schottky contact with the Schottky layer 327, and ohmic electrodes 340 are formed on the n+-type GaAs cap layer 328.
摘要翻译：一种半导体器件及其制造方法。半导体器件具有半绝缘GaAs衬底310，形成在半绝缘GaAs衬底310上的GaAs缓冲层321，AlGaAs缓冲层322，沟道层323，间隔层324，载流子供应层325，间隔层326，由未掺杂的In 0.48 Ga 0.52 P材料构成的肖特基层327和n + 栅电极330形成在肖特基层327上，由LaB 6构成，与肖特基层327具有肖特基接触，并且欧姆电极340形成在第n + +型GaAs覆盖层328。

15. 发明授权

US06570464B1 High frequency apparatus 失效
标题翻译：高频设备
公开(公告)号：US06570464B1
公开(公告)日：2003-05-27
申请号：US09648498
申请日：2000-08-25
申请人： Mitsuru Tanabe , Mitsuru Nishitsuji , Yoshiharu Anda
发明人： Mitsuru Tanabe , Mitsuru Nishitsuji , Yoshiharu Anda
IPC分类号： H01P500
CPC分类号： H01P3/003 , H01P11/003
摘要： A high frequency apparatus includes a dielectric substrate having a surface including a first area and at least one second area; a first dielectric thin layer provided on a portion of a first area; and a uniplanar transmission line provided on the first dielectric thin layer and on a portion of the second area, the uniplanar transmission line extending, continuously on the second area and the first dielectric thin layer.
摘要翻译：高频装置包括具有包括第一区域和至少一个第二区域的表面的电介质基板; 设置在第一区域的一部分上的第一电介质薄层; 以及设置在所述第一电介质薄层上和所述第二区域的一部分上的所述单面传输线，所述单面传输线在所述第二区域和所述第一电介质薄层上连续地延伸。

16. 发明授权

US06300190B1 Method for fabricating semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US06300190B1
公开(公告)日：2001-10-09
申请号：US09452389
申请日：1999-12-01
申请人： Mitsuru Nishitsuji , Yoshiharu Anda , Katsuhiko Kawashima , Tsuyoshi Tanaka
发明人： Mitsuru Nishitsuji , Yoshiharu Anda , Katsuhiko Kawashima , Tsuyoshi Tanaka
IPC分类号： H01L218242
CPC分类号： H01L29/66863 , H01L21/28587 , H01L27/0629
摘要： First, an insulating film is formed over the entire surface of a semiconductor substrate including a channel region for a field effect transistor. The insulating film has a gate electrode opening over the channel region. Next, a protective film is deposited over the entire surface of the insulating film. Then, a lower electrode, a capacitive insulating film and an upper electrode are formed in this order in a region on the protective film where a capacitor will be formed. Subsequently, part of the protective film, with which the gate electrode opening of the insulating film has been filled in, is removed, thereby exposing the semiconductor substrate within the gate electrode opening. And then a gate electrode is formed to fill in the gate electrode opening again.
摘要翻译：首先，在包括场效应晶体管的沟道区域的半导体衬底的整个表面上形成绝缘膜。绝缘膜具有在沟道区域上开口的栅电极。接下来，在绝缘膜的整个表面上沉积保护膜。然后，在保护膜上将形成电容器的区域中，依次形成下电极，电容绝缘膜和上电极。随后，去除绝缘膜的栅电极开口已经填充的保护膜的一部分，从而使半导体衬底暴露在栅电极开口内。然后形成栅电极以再次填充栅电极开口。

17. 发明授权

US6153499A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6153499A
公开(公告)日：2000-11-28
申请号：US289946
申请日：1999-04-13
申请人： Yoshiharu Anda , Toshinobu Matsuno , Katsunori Nishii , Kaoru Inoue , Manabu Yanagihara , Mitsuru Tanabe
发明人： Yoshiharu Anda , Toshinobu Matsuno , Katsunori Nishii , Kaoru Inoue , Manabu Yanagihara , Mitsuru Tanabe
IPC分类号： H01L21/28 , H01L21/027 , H01L21/285 , H01L21/338 , H01L21/768 , H01L29/812 , H01L21/44
CPC分类号： H01L21/28581 , H01L21/0271 , H01L21/0277 , H01L21/76816 , Y10S438/949
摘要： A first resist film for EB exposure, a buffer film, and a second resist film for i-line exposure are applied sequentially onto a substrate. Thereafter, the second resist film and the buffer film are subjected to patterning for forming a first opening. Then, dry etching is performed with respect to the first resist film masked with the second resist film to transfer the pattern of the second resist film to the first resist film and thereby form a second opening in the first resist film. Subsequently, a third resist film of chemically amplified type is applied to the entire surface of the first resist film to form a mixing layer in conjunction with the first resist film. As a result, the wall faces of the second opening are covered with the mixing layer and the width of the second opening is thereby reduced.
摘要翻译：用于EB曝光的第一抗蚀剂膜，缓冲膜和用于i线曝光的第二抗蚀剂膜顺序地施加到基板上。此后，对第二抗蚀剂膜和缓冲膜进行用于形成第一开口的图案化。然后，相对于用第二抗蚀剂膜掩蔽的第一抗蚀剂膜进行干蚀刻，将第二抗蚀剂膜的图案转印到第一抗蚀剂膜上，从而在第一抗蚀剂膜中形成第二开口。随后，将化学放大型的第三抗蚀剂膜施加到第一抗蚀剂膜的整个表面上以与第一抗蚀剂膜结合形成混合层。结果，第二开口的壁面被混合层覆盖，从而减小了第二开口的宽度。

18. 发明授权

US06051454A Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06051454A
公开(公告)日：2000-04-18
申请号：US151357
申请日：1998-09-10
申请人： Yoshiharu Anda , Toshinobu Matsuno , Manabu Yanagihara , Mitsuru Tanabe , Toshiaki Matsui , Nobumitsu Hirose
发明人： Yoshiharu Anda , Toshinobu Matsuno , Manabu Yanagihara , Mitsuru Tanabe , Toshiaki Matsui , Nobumitsu Hirose
IPC分类号： H01L21/285 , H01L21/335 , H01L21/338
CPC分类号： H01L29/66462 , H01L21/28587 , Y10S438/95
摘要： A lower resist film, which is made of PMMA for EB exposure and has a thickness of about 200 nm, is applied onto a substrate, and then an upper resist film to be exposed to i-rays is applied on the lower resist film. Thereafter, a mixed layer, in which the upper and lower resist films are mixed, is formed in the interface between the upper and lower resist films. Next, the upper resist film, except for the head-forming region thereof, is exposed to i-rays and developed, thereby forming an upper-layer opening. And then the mixed layer and a leg-forming region of the lower resist film are exposed to EB and developed, thereby forming a lower-layer opening having an upper part like a taper progressively expanding upward.
摘要翻译：将用于EB曝光的PMMA制成并具有约200nm厚度的较低抗蚀剂膜施加到基板上，然后在下抗蚀剂膜上施加暴露于i射线的上抗蚀剂膜。此后，在上下抗蚀剂膜之间的界面中形成混合有上下抗蚀剂膜的混合层。接下来，将除了其头部形成区域之外的上抗蚀剂膜暴露于i射线并显影，从而形成上层开口。然后将下层抗蚀剂膜的混合层和腿部形成区域暴露于EB并显影，从而形成具有逐渐向上扩展的锥形的上部的下层开口。

19. 发明授权

US07829957B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07829957B2
公开(公告)日：2010-11-09
申请号：US12054800
申请日：2008-03-25
申请人： Yoshiaki Kato , Yoshiharu Anda , Akihiko Nishio
发明人： Yoshiaki Kato , Yoshiharu Anda , Akihiko Nishio
IPC分类号： H01L29/76
CPC分类号： H01L29/7783 , H01L21/8252 , H01L27/0605 , H01L27/0883
摘要： A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer.
摘要翻译：包括E-FET和D-FET两者的半导体器件，并且可以有助于控制E-FET中的Vth，并抑制Vf的降低，并且提供其制造方法。在同一半导体衬底上包括E-FET和D-FET的半导体器件包括：用于调节E-FET的阈值的第一阈值调整层; 形成在第一阈值调整层上的第一蚀刻停止层; 所述第二阈值调整层形成在所述第一蚀刻停止层上，用于调节所述D-FET的阈值; 形成在所述第二阈值调整层上的第二蚀刻停止层; 穿过与第一阈值调整层接触的第一蚀刻停止层，第二阈值调节层和第二蚀刻阻挡层的第一栅电极; 并且所述第二栅电极贯穿与所述第二阈值调整层接触的所述第二蚀刻停止层。

20. 发明授权

US07495268B2 Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07495268B2
公开(公告)日：2009-02-24
申请号：US11757533
申请日：2007-06-04
申请人： Yoshiaki Kato , Yoshiharu Anda , Akiyoshi Tamura
发明人： Yoshiaki Kato , Yoshiharu Anda , Akiyoshi Tamura
IPC分类号： H01L29/812
CPC分类号： H01L29/8128 , H01L29/42316 , H01L29/66863 , H01L29/778
摘要： A semiconductor device according to the present invention includes: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate electrode formed on the first Schottky layer to form a Schottky barrier junction with the first Schottky layer; a first source electrode and a first drain electrode formed so as to sandwich the first gate electrode and electrically connected to the channel layer; a second gate electrode formed on the second Schottky layer and made of a material different from the first gate electrode to form a Schottky barrier junction with the second Schottky layer; and a second source electrode and a second drain electrode formed so as to sandwich the second gate electrode and electrically connected to the channel layer.
摘要翻译：根据本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的沟道层; 在沟道层上形成的施主层; 形成在供体层上的第一肖特基层; 形成在第一肖特基层上的第二肖特基层; 形成在所述第一肖特基层上以与所述第一肖特基层形成肖特基势垒结的第一栅电极; 第一源电极和第一漏电极，其形成为夹着所述第一栅电极并电连接到所述沟道层; 第二栅电极，形成在所述第二肖特基层上，并且由与所述第一栅电极不同的材料制成，以与所述第二肖特基层形成肖特基势垒结; 以及第二源电极和第二漏电极，其形成为夹着所述第二栅极并电连接到所述沟道层。

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