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    • 2. 发明授权
    • Semiconductor device and manufacturing method thereof
    • 半导体装置及其制造方法
    • US07829957B2
    • 2010-11-09
    • US12054800
    • 2008-03-25
    • Yoshiaki KatoYoshiharu AndaAkihiko Nishio
    • Yoshiaki KatoYoshiharu AndaAkihiko Nishio
    • H01L29/76
    • H01L29/7783H01L21/8252H01L27/0605H01L27/0883
    • A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer.
    • 包括E-FET和D-FET两者的半导体器件,并且可以有助于控制E-FET中的Vth,并抑制Vf的降低,并且提供其制造方法。 在同一半导体衬底上包括E-FET和D-FET的半导体器件包括:用于调节E-FET的阈值的第一阈值调整层; 形成在第一阈值调整层上的第一蚀刻停止层; 所述第二阈值调整层形成在所述第一蚀刻停止层上,用于调节所述D-FET的阈值; 形成在所述第二阈值调整层上的第二蚀刻停止层; 穿过与第一阈值调整层接触的第一蚀刻停止层,第二阈值调节层和第二蚀刻阻挡层的第一栅电极; 并且所述第二栅电极贯穿与所述第二阈值调整层接触的所述第二蚀刻停止层。
    • 3. 发明申请
    • Semiconductor resistor and method for manufacturing the same
    • 半导体电阻及其制造方法
    • US20060076585A1
    • 2006-04-13
    • US11234172
    • 2005-09-26
    • Yoshiaki KatoYoshiharu AndaAkiyoshi Tamura
    • Yoshiaki KatoYoshiharu AndaAkiyoshi Tamura
    • H01L31/112
    • H01L27/0605H01L27/0629
    • An object of the present invention is to provide a semiconductor resistor that allows improvement in saturation voltage characteristics and a method for manufacturing the same. The semiconductor resistor of the present invention is formed on the substrate on which a GaAs FET is formed. The GaAs FET includes: a channel layer; a Schottky layer formed on the channel layer and made of undoped InGaP; and a contact layer formed on the Schottky layer. The semiconductor resistor includes: a contact layer including a part of the contact layer isolated from the GaAs FET; an active region including a part of the Schottky layer and a part of the channel layer, both of which are isolated from the GaAs FET; and two ohmic electrodes formed on the contact layer, and the Schottky layer isolated from the GaAs FET is exposed in an area between the two ohmic electrodes.
    • 本发明的一个目的是提供一种允许提高饱和电压特性的半导体电阻器及其制造方法。 本发明的半导体电阻器形成在其上形成有GaAs FET的基板上。 GaAs FET包括:沟道层; 形成在沟道层上并由未掺杂的InGaP制成的肖特基层; 以及形成在肖特基层上的接触层。 半导体电阻器包括:接触层,其包括与GaAs FET隔离的部分接触层; 包括肖特基层的一部分和沟道层的一部分的有源区域,两者都与GaAs FET隔离; 并且形成在接触层上的两个欧姆电极,并且从GaAs FET隔离的肖特基层暴露在两个欧姆电极之间的区域中。
    • 4. 发明授权
    • Semiconductor device and manufacturing method of the same
    • 半导体器件及其制造方法相同
    • US07495268B2
    • 2009-02-24
    • US11757533
    • 2007-06-04
    • Yoshiaki KatoYoshiharu AndaAkiyoshi Tamura
    • Yoshiaki KatoYoshiharu AndaAkiyoshi Tamura
    • H01L29/812
    • H01L29/8128H01L29/42316H01L29/66863H01L29/778
    • A semiconductor device according to the present invention includes: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate electrode formed on the first Schottky layer to form a Schottky barrier junction with the first Schottky layer; a first source electrode and a first drain electrode formed so as to sandwich the first gate electrode and electrically connected to the channel layer; a second gate electrode formed on the second Schottky layer and made of a material different from the first gate electrode to form a Schottky barrier junction with the second Schottky layer; and a second source electrode and a second drain electrode formed so as to sandwich the second gate electrode and electrically connected to the channel layer.
    • 根据本发明的半导体器件包括:半导体衬底; 形成在所述半导体衬底上的沟道层; 在沟道层上形成的施主层; 形成在供体层上的第一肖特基层; 形成在第一肖特基层上的第二肖特基层; 形成在所述第一肖特基层上以与所述第一肖特基层形成肖特基势垒结的第一栅电极; 第一源电极和第一漏电极,其形成为夹着所述第一栅电极并电连接到所述沟道层; 第二栅电极,形成在所述第二肖特基层上,并且由与所述第一栅电极不同的材料制成,以与所述第二肖特基层形成肖特基势垒结; 以及第二源电极和第二漏电极,其形成为夹着所述第二栅极并电连接到所述沟道层。
    • 7. 发明授权
    • Photoelectric encoder
    • 光电编码器
    • US08325066B2
    • 2012-12-04
    • US13025198
    • 2011-02-11
    • Yoshiaki Kato
    • Yoshiaki Kato
    • H03M1/22
    • G01D5/24476
    • A photoelectric encoder includes: a scale having a grating formed with a predetermined period Ps; and a detector head being movable relative to the scale and including a light source and a light receiving unit. In a configuration where light receiving elements in the light receiving unit output N-points light and dark signals (N is an integer of 3 or more), and where phases of the N-points light and dark signals are detected by a least-squares method to fit a sinusoidal function with fixed period to N-points digital signals digitized from the N-points light and dark signals, an N-points light and dark signal period P is set at an integral multiple of a data-point interval w of the N-points digital signals, and an overall length M of the light receiving elements is set at an integral multiple of the N-points light and dark signal period P. Thereby, position detecting errors occurring due to a stain of the scale and/or a defect in the grating can be reduced by simple computing.
    • 光电编码器包括:具有形成有预定周期Ps的光栅的刻度; 以及检测器头,其相对于刻度尺可移动,并且包括光源和光接收单元。 在光接收单元中的光接收元件输出N点光暗信号(N为3以上的整数)的情况下,通过最小二乘法来检测N点光暗信号的相位 将具有固定周期的正弦函数拟合为从N点光暗信号数字化的N点数字信号的方法,将N点光暗信号周期P设定为数据点间隔w的整数倍 N点数字信号和光接收元件的总长度M被设定为N点光暗信号周期P的整数倍。由此,由于刻度和/ 或者可以通过简单的计算来减少光栅中的缺陷。
    • 9. 发明授权
    • Solid-state imaging device, driving method thereof, and camera
    • 固态成像装置,其驱动方法和相机
    • US08085331B2
    • 2011-12-27
    • US12330050
    • 2008-12-08
    • Yoshiaki KatoAkiyoshi KohnoHiroshi MatsumotoTakeshi Fujita
    • Yoshiaki KatoAkiyoshi KohnoHiroshi MatsumotoTakeshi Fujita
    • H04N5/335
    • H04N5/335H04N5/372H04N5/3765
    • An objective of the present invention is to provide the solid-state imaging device and the driving method thereof which can control: a poor picture quality, such as blooming, to maximize a dynamic range of the photodiode; and a poor picture quality resulted from an incomplete read-out operation. A solid-state imaging device in the present invention includes: a solid-state imaging element; and a driving pulse controlling unit applying a driving pulse to each of read-out gates of a column CCD. The driving pulse controlling unit transfers in a column direction signal charge within a charge transfer region of the column CCD by applying a column transfer clock having a LOW level voltage and a MIDDLE level voltage, and the LOW level voltage and the MIDDLE level voltage are minus voltages.
    • 本发明的目的是提供一种可以控制如图像质量差的固态成像装置及其驱动方法,以使光电二极管的动态范围最大化; 并且由于读取操作不完整导致的图像质量差。 本发明的固态成像装置包括:固态成像元件; 以及驱动脉冲控制单元,将驱动脉冲施加到列CCD的每个读出门。 驱动脉冲控制单元通过施加具有低电平电压和中等电平的列传送时钟,在列CCD的电荷传送区域内的列方向上传送信号电荷,并且低电平电压和中间电平电压为负 电压。
    • 10. 发明授权
    • Method for driving solid-state imaging apparatus and solid-state imaging apparatus
    • 用于驱动固态成像装置和固态成像装置的方法
    • US07884872B2
    • 2011-02-08
    • US11483746
    • 2006-07-10
    • Tsuyoshi HasukaRyoichi NagayoshiKeijirou ItakuraIzumi ShimizuYoshiaki Kato
    • Tsuyoshi HasukaRyoichi NagayoshiKeijirou ItakuraIzumi ShimizuYoshiaki Kato
    • H04N5/335
    • H04N5/3592
    • A driving method is applied to a solid-state imaging apparatus having photoelectric conversion portions, transfer portion for reading out signal charges, and an excess charge draining portion for draining charges exceeding a saturation charge amount that is set by a reference voltage. One of driving modes is selected from a full pixel mode in which accumulated signal charges are detected individually for each pixel and a pixel mixing mode in which signal charges of a predetermined number of pixels are mixed to be detected. In the full pixel mode, the draining portion is supplied with the reference voltage having the same value during a charge accumulation period and a read transfer period for read transferring charges. In the pixel mixing mode, the draining portion is supplied with the reference voltage having a low level during the charge accumulation period and the reference voltage having a high level during the read transfer period. An appropriate driving for the pixel mixing mode can be performed by avoiding a limitation of a substrate voltage, without deteriorating the spectral characteristics, the sensitivity, nor the linearity.
    • 将驱动方法应用于具有光电转换部分的固态成像装置,用于读出信号电荷的转印部分和用于排出超过由参考电压设置的饱和电荷量的电荷的过量电荷排出部分。 其中一种驱动模式是从满像素模式中选择的,其中针对每个像素分别检测累积的信号电荷,以及混合预定数量的像素的信号电荷进行检测的像素混合模式。 在全像素模式中,在电荷累积期间和读取传输电荷的读取传送周期中,向排水部分提供具有相同值的参考电压。 在像素混合模式中,在读取传送周期期间,在电荷累积期间内,向排水部分供给具有低电平的参考电压。 可以通过避免衬底电压的限制而不劣化光谱特性,灵敏度和线性度来进行像素混合模式的适当驱动。