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    • 1. 发明申请
    • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    • 半导体器件及其制造方法
    • US20080251837A1
    • 2008-10-16
    • US12054800
    • 2008-03-25
    • Yoshiaki KATOYoshiharu ANDAAkihiko NISHIO
    • Yoshiaki KATOYoshiharu ANDAAkihiko NISHIO
    • H01L21/04H01L49/00
    • H01L29/7783H01L21/8252H01L27/0605H01L27/0883
    • A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer.
    • 包括E-FET和D-FET两者的半导体器件,并且可以有助于控制E-FET中的Vth,并抑制Vf的降低,并且提供其制造方法。 在同一半导体衬底上包括E-FET和D-FET的半导体器件包括:用于调节E-FET的阈值的第一阈值调整层; 形成在第一阈值调整层上的第一蚀刻停止层; 所述第二阈值调整层形成在所述第一蚀刻停止层上,用于调节所述D-FET的阈值; 形成在所述第二阈值调整层上的第二蚀刻停止层; 穿过与第一阈值调整层接触的第一蚀刻停止层,第二阈值调节层和第二蚀刻阻挡层的第一栅电极; 并且所述第二栅电极贯穿与所述第二阈值调整层接触的所述第二蚀刻停止层。
    • 2. 发明申请
    • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    • 半导体器件及其制造方法
    • US20090230482A1
    • 2009-09-17
    • US12404562
    • 2009-03-16
    • Yoshiaki KATOYoshiharu ANDAAkiyoshi TAMURA
    • Yoshiaki KATOYoshiharu ANDAAkiyoshi TAMURA
    • H01L27/088H01L21/28
    • H01L27/0605H01L27/0883H01L29/66462H01L29/7783
    • A semiconductor device in which an E-FET and a D-FET are integrated on the same substrate, wherein an epitaxial layer includes, in the following order from the semiconductor substrate: a first threshold adjustment layer that adjusts a threshold voltage of a gate of the E-FET and a threshold voltage of a gate of the D-FET; a first etching-stopper layer that stops etching performed from an uppermost layer to a layer abutting on the first etching-stopper layer; a second threshold adjustment layer that adjusts the threshold voltage of the gate of the D-FET; and a second etching-stopper layer that stops the etching performed from the uppermost layer to a layer abutting on the second etching-stopper layer, and at least one of the first etching-stopper layer and the second threshold adjustment layer includes an n-type doped region.
    • 一种半导体器件,其中E-FET和D-FET集成在同一衬底上,其中外延层从半导体衬底按以下顺序包括:第一阈值调节层,其调节栅极的阈值电压 E-FET和D-FET的栅极的阈值电压; 第一蚀刻停止层,其停止从最上层到邻接于所述第一蚀刻停止层的层的蚀刻; 调节D-FET的栅极的阈值电压的第二阈值调整层; 以及第二蚀刻停止层,其将从最上层进行的蚀刻停止到与第二蚀刻停止层相邻的层,并且第一蚀刻停止层和第二阈值调整层中的至少一个包括n型 掺杂区域。
    • 3. 发明申请
    • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    • 半导体器件及其制造方法
    • US20070295991A1
    • 2007-12-27
    • US11757533
    • 2007-06-04
    • Yoshiaki KATOYoshiharu ANDAAkiyoshi TAMURA
    • Yoshiaki KATOYoshiharu ANDAAkiyoshi TAMURA
    • H01L29/812H01L21/338
    • H01L29/8128H01L29/42316H01L29/66863H01L29/778
    • A semiconductor device according to the present invention includes: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate electrode formed on the first Schottky layer to form a Schottky barrier junction with the first Schottky layer; a first source electrode and a first drain electrode formed so as to sandwich the first gate electrode and electrically connected to the channel layer; a second gate electrode formed on the second Schottky layer and made of a material different from the first gate electrode to form a Schottky barrier junction with the second Schottky layer; and a second source electrode and a second drain electrode formed so as to sandwich the second gate electrode and electrically connected to the channel layer.
    • 根据本发明的半导体器件包括:半导体衬底; 形成在所述半导体衬底上的沟道层; 在沟道层上形成的施主层; 形成在供体层上的第一肖特基层; 形成在第一肖特基层上的第二肖特基层; 形成在所述第一肖特基层上以与所述第一肖特基层形成肖特基势垒结的第一栅电极; 第一源电极和第一漏电极,其形成为夹着所述第一栅电极并电连接到所述沟道层; 第二栅电极,形成在所述第二肖特基层上,并且由与所述第一栅电极不同的材料制成,以与所述第二肖特基层形成肖特基势垒结; 以及第二源电极和第二漏电极,其形成为夹着所述第二栅极并电连接到所述沟道层。
    • 4. 发明申请
    • FIELD-EFFECT TRANSISTOR
    • 场效应晶体管
    • US20110227132A1
    • 2011-09-22
    • US13118945
    • 2011-05-31
    • Yoshiharu ANDAHidetoshi ISHIDATetsuzo UEDA
    • Yoshiharu ANDAHidetoshi ISHIDATetsuzo UEDA
    • H01L29/205
    • H01L29/42316H01L29/2003H01L29/4236H01L29/7787
    • The present invention has as an object to provide a FET having low on-resistance. The FET according to the present invention includes: first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a higher band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and having a higher band gap energy than the third nitride semiconductor layer. A channel is formed in a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer.
    • 本发明的目的是提供一种具有低导通电阻的FET。 根据本发明的FET包括:第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更高的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上的第三氮化物半导体层; 形成在所述第三氮化物半导体层上并且具有比所述第三氮化物半导体层更高的带隙能量的第四氮化物半导体层。 在第一氮化物半导体层和第二氮化物半导体层之间的异质结界面形成沟道。