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11. 发明授权

US07400206B2 Clock circuit with programmable load capacitors 失效
标题翻译：具有可编程负载电容的时钟电路
公开(公告)号：US07400206B2
公开(公告)日：2008-07-15
申请号：US11089857
申请日：2005-03-24
申请人： Wenjung Sheng , Shyam S. Somayajula , Xue-Mei Gong
发明人： Wenjung Sheng , Shyam S. Somayajula , Xue-Mei Gong
IPC分类号： H03B5/12
CPC分类号： H03K3/0307 , H03B5/36 , H03B2201/0266 , H03K3/012
摘要： In one embodiment, the present invention includes methods and apparatus for providing initial control values to programmable load capacitors of an oscillator, such as that of a real time clock circuit. Using the initial values, the real time clock circuit may begin operation, enabling additional circuitry within an integrated circuit to begin operation. This additional circuitry may cause operating values to program the load capacitors to provide a desired reference clock based on a given system's requirements.
摘要翻译：在一个实施例中，本发明包括用于向诸如实时时钟电路的振荡器的可编程负载电容器提供初始控制值的方法和装置。使用初始值，实时时钟电路可以开始运行，使集成电路中的附加电路能够开始运行。这个额外的电路可以使操作值对负载电容器进行编程，以根据给定的系统要求提供所需的参考时钟。

12. 发明授权

US5801652A Pattern dependent noise reduction in a digital processing circuit utilizing image circuitry 失效
标题翻译：利用图像电路的数字处理电路中的模式相关噪声降低
公开(公告)号：US5801652A
公开(公告)日：1998-09-01
申请号：US735573
申请日：1996-10-23
申请人： Xue Mei Gong
发明人： Xue Mei Gong
IPC分类号： G06F3/05 , G06F17/18 , H03M1/12 , H03M3/00 , H03M3/02 , H03M1/00 , H03M1/36
CPC分类号： G06F17/18 , H03M3/35 , H03M3/332 , H03M3/43 , H03M3/458 , H03M3/50
摘要： A delta-sigma analog/digital converter is provided for operating in the analog domain to generate a digital value that is to be processed by a digital signal processor (DSP) (26) to provide on the output a digital output. Each data node in each processing element in the DSP (26) is mirrored by the way of a corresponding data node in the mirror circuit (36). This results in the addition of noise via a noise adder (28) such that each data node in the main portion of the DSP (26) that can draw current from the power supply during a transition will have a corresponding complement node in the mirror circuit (36). Each data node in the mirror circuit will add noise via a transition drawing current from the power supply whenever the transition does not occur at the corresponding data node in the main portion of the DSP (26). Therefore, di/dt noise will be added for each cycle, regardless of the data pattern. This is effected by insuring that, for each data cycle, each data node undergoes a positive and a negative transition. By using a return-to-zero data stream, i.e., inserting a zero in each cycle at each data node, a positive transition and a negative transition can be during each data cycle.
摘要翻译：提供了一个Δ-Σ模拟/数字转换器，用于在模拟域中操作以产生要由数字信号处理器（DSP）（26）处理的数字值，以在输出端提供数字输出。 DSP（26）中的每个处理元件中的每个数据节点通过镜像电路（36）中对应的数据节点的方式进行镜像。这导致通过噪声加法器（28）增加噪声，使得在转换期间能够从电源抽取电流的DSP（26）的主要部分中的每个数据节点将在镜像电路中具有对应的补码节点（36）。只要在DSP（26）的主要部分中的对应数据节点处不发生转换，镜像电路中的每个数据节点将通过来自电源的转换绘制电流来增加噪声。因此，无论数据模式如何，都会为每个周期添加di / dt噪声。这通过确保对于每个数据周期，每个数据节点经历正和负转换来实现。通过使用归零数据流，即在每个数据节点处在每个周期中插入零，可以在每个数据周期期间进行正转换和负转换。

13. 发明申请

US20140055179A1 INTERPOLATIVE DIVIDER LINEARITY ENHANCEMENT TECHNIQUES 有权
标题翻译：插入式线性增强技术
公开(公告)号：US20140055179A1
公开(公告)日：2014-02-27
申请号：US13592160
申请日：2012-08-22
申请人： Xue-Mei Gong , Adam B. Eldredge , Susumu Hara
发明人： Xue-Mei Gong , Adam B. Eldredge , Susumu Hara
IPC分类号： H03L7/06
CPC分类号： H03L7/1976 , H03L7/081 , H03L7/104
摘要： A flexible clock synthesizer technique includes generating a phase interpolator calibration signal to adjust a phase interpolator output signal generated by a phase interpolator of an interpolative divider. The phase interpolator is responsive to a phase interpolator control code and an output signal of a fractional-N divider of the interpolative divider. The phase interpolator calibration signal is based on an error signal indicative of a phase interpolator error. The error signal may indicate a phase relationship between a reference clock signal and a feedback clock signal of a PLL. The interpolative divider may be coupled in a feedback path of the PLL. The PLL may receive a reference clock signal and the feedback clock signal may be an adjusted phase interpolator output signal. The phase interpolator calibration signal may be a phase interpolator offset code corresponding to the phase interpolator control code or a phase interpolator gain signal.
摘要翻译：灵活的时钟合成器技术包括产生相位内插器校准信号以调整由内插分频器的相位插值器产生的相位内插器输出信号。相位插值器响应于内插分频器的分数N分频器的相位内插器控制代码和输出信号。相位内插器校准信号基于指示相位内插器误差的误差信号。误差信号可以指示PLL的参考时钟信号和反馈时钟信号之间的相位关系。内插分压器可以耦合在PLL的反馈路径中。 PLL可以接收参考时钟信号，并且反馈时钟信号可以是调整的相位内插器输出信号。相位内插器校准信号可以是与相位内插器控制代码或相位内插器增益信号相对应的相位内插器偏移代码。

14. 发明申请

US20080189565A1 Automatically switching power supply sources for a clock circuit 有权
标题翻译：自动切换时钟电路的电源
公开(公告)号：US20080189565A1
公开(公告)日：2008-08-07
申请号：US12079565
申请日：2008-03-27
申请人： Wenjung Sheng , Shyam S. Somayajula , Xue-Mei Gong
发明人： Wenjung Sheng , Shyam S. Somayajula , Xue-Mei Gong
IPC分类号： G06F1/00
CPC分类号： G06F1/04 , G06F1/263
摘要： In one embodiment, a power supply switching circuit may automatically provide power to a clock circuit from one of an auxiliary power supply and a main power supply, based on a voltage of the main power supply. To provide automatic switching, a switch circuit coupled between the power supplies and the clock circuit may be controlled by a voltage detector, in some embodiments.
摘要翻译：在一个实施例中，电源开关电路可以基于主电源的电压自动地向辅助电源和主电源之一提供电力到时钟电路。为了提供自动切换，在一些实施例中，耦合在电源和时钟电路之间的开关电路可以由电压检测器控制。

15. 发明授权

US07370214B2 Automatically switching power supply sources for a clock circuit 有权
公开(公告)号：US07370214B2
公开(公告)日：2008-05-06
申请号：US11089836
申请日：2005-03-24
申请人： Wenjung Sheng , Shyam S. Somayajula , Xue-Mei Gong
发明人： Wenjung Sheng , Shyam S. Somayajula , Xue-Mei Gong
IPC分类号： G06F1/00 , G06F11/30
CPC分类号： G06F1/04 , G06F1/263
摘要： In one embodiment, a power supply switching circuit may automatically provide power to a clock circuit from one of an auxiliary power supply and a main power supply, based on a voltage of the main power supply. To provide automatic switching, a switch circuit coupled between the power supplies and the clock circuit may be controlled by a voltage detector, in some embodiments.

16. 发明授权

US07227484B2 Startup apparatus and technique for a wireless system that uses time domain isolation 有权
标题翻译：使用时域隔离的无线系统的启动装置和技术
公开(公告)号：US07227484B2
公开(公告)日：2007-06-05
申请号：US11172213
申请日：2005-06-29
申请人： David O. Anderton , Jeffrey L. Yiin , Xue-Mei Gong
发明人： David O. Anderton , Jeffrey L. Yiin , Xue-Mei Gong
IPC分类号： H03M1/66
CPC分类号： H04B15/00 , H04B1/40
摘要： A technique includes providing a butter to receive data from a processor of a wireless device in response to an active mode of the processor and selectively coupling an input terminal of a filter to the buffer based on a status of the buffer. The techniciue may be used with a wireless system that includes a digital signal processor, a buffer, a wireless interface and a switch. The buffer receives data from the digital signal processor in response to an active mode of the digital signal processor. The switch selectively couples a terminal of the wireless interface to the buffer in response to a determination of a status of the buffer.
摘要翻译：一种技术包括提供黄油以响应于处理器的活动模式从无线设备的处理器接收数据，并且基于缓冲器的状态选择性地将过滤器的输入端子耦合到缓冲器。该技术可以与包括数字信号处理器，缓冲器，无线接口和开关的无线系统一起使用。缓冲器响应于数字信号处理器的活动模式从数字信号处理器接收数据。响应于确定缓冲器的状态，开关选择性地将无线接口的终端耦合到缓冲器。

17. 发明申请

US20070001884A1 Startup apparatus and technique for a wireless system that uses time domain isolation 有权
标题翻译：使用时域隔离的无线系统的启动装置和技术
公开(公告)号：US20070001884A1
公开(公告)日：2007-01-04
申请号：US11172213
申请日：2005-06-29
申请人： David Anderton , Jeffrey Yiin , Xue-Mei Gong
发明人： David Anderton , Jeffrey Yiin , Xue-Mei Gong
IPC分类号： H03M1/66
CPC分类号： H04B15/00 , H04B1/40
摘要： A technique that includes providing a buffer to receive data from a processor of a wireless device in response to an active mode of the processor and selectively coupling an input terminal of a filter to the buffer based on a status of the buffer.
摘要翻译：一种技术，其包括提供缓冲器以响应于处理器的活动模式从无线设备的处理器接收数据，并且基于缓冲器的状态选择性地将过滤器的输入端子耦合到缓冲器。

18. 发明授权

US06271780B1 Gain ranging analog-to-digital converter with error correction 有权
标题翻译：增益范围模数转换器，具有纠错功能
公开(公告)号：US06271780B1
公开(公告)日：2001-08-07
申请号：US09168601
申请日：1998-10-08
申请人： Xue-Mei Gong , Ka Yin Leung , Eric J. Swanson
发明人： Xue-Mei Gong , Ka Yin Leung , Eric J. Swanson
IPC分类号： H03H188
CPC分类号： H03M3/488 , H04R3/00
摘要： A gain ranging AD converter is provided having two separate gain paths. There is provided a low-gain path and a high-gain path. The low gain path is processed through an analog modulator (333) and then through a filter section to provide on an output of a high-pass filter (339), a low-gain signal which is then compensated for in an equalizer section (347). This equalizing section (347) calibrates the output signal to ensure that the difference between the calibrated signal and the high-gain signal differs only by the fixed gain between the two paths. The high-gain path also includes a modulator (335) for processing through a filter section to provide on the output of a high-pass filter section (343) a high-gain signal. A calibration generator (361) is utilized to generate the parameters for performing the equalization. This calibration generator (361) utilizes both phase and amplitude information from the high-gain path and from both the calibrated low-gain path to generate the calibration parameters for use by the equalizing section (347). Thereafter, the mixing operation is performed to provide a “blend” before summing with a summing junction (351).
摘要翻译：增益测距AD转换器具有两个独立的增益路径。提供了低增益路径和高增益路径。通过模拟调制器（333）处理低增益路径，然后通过滤波器部分提供高通滤波器（339）的输出，然后在均衡器部分（347）中对低增益信号进行补偿）。该均衡部分（347）校准输出信号，以确保校准信号和高增益信号之间的差异仅仅在两条路径之间的固定增益之间不同。高增益路径还包括用于通过滤波器部分处理以在高通滤波器部分（343）的输出上提供高增益信号的调制器（335）。校准发生器（361）用于产生用于执行均衡的参数。该校准发生器（361）利用来自高增益路径的相位和幅度信息以及来自校准的低增益路径的两个相位和幅度信息来生成用于均衡部分（347）的校准参数。此后，执行混合操作以在与求和结（351）相加之前提供“混合”。

19. 发明授权

US6057793A Digital decimation filter and method for achieving fractional data rate reduction with minimal hardware or software overhead 失效
$Digital decimation filter and method for achieving fractional data rate reduction with minimal hardware or software overhead$
公开(公告)号：US6057793A
公开(公告)日：2000-05-02
申请号：US97141
申请日：1998-06-12
申请人： Xue-Mei Gong , Tim J. Dupuis , Jinghui Lu , Korhan Titizer
发明人： Xue-Mei Gong , Tim J. Dupuis , Jinghui Lu , Korhan Titizer
IPC分类号： H03H17/04 , H03M3/00
CPC分类号： H03H17/0671
摘要： An analog-to-digital converter is provided for producing digital signal representative of analog signals. Noise induced upon the digital signals can be substantially removed using a digital decimation filter. The decimation filter includes a front-end portion which receives the digital data at a relatively high sample rate and performs filtering operations with minimal complexity. Preferably, the front-end portion includes at least one stage of filtering and more preferably at least two filter stages, each of which perform interpolation separate from decimation. According to one embodiment, the first stage of the front-end portion involves decimation and the latter stage or stages of that portion involves a combination of interpolation and decimation. The cumulative effect is to reduce the sample rate of the incoming data stream produced by, for example, a quantizer to a value which can be more easily manipulated by the back-end portion of the digital decimation filter. The front-end portion can therefore reduce the data rate change factor K to a smaller, fixed integer data rate change factor K.sub.1, regardless of whether data rate change factor K is an integer number or involves a fractional number.

20. 发明授权

US5719572A Digital signal processor with reduced pattern dependent noise 失效
标题翻译：数字信号处理器具有减少的图形相关噪声
公开(公告)号：US5719572A
公开(公告)日：1998-02-17
申请号：US735574
申请日：1996-10-23
申请人： Xue Mei Gong
发明人： Xue Mei Gong
IPC分类号： H03M3/02 , H03M1/00 , H03M1/06
CPC分类号： H03M3/332 , H03M3/35 , H03M3/43 , H03M3/458 , H03M3/50
摘要： A delta-sigma analog/digital converter is provided for operating in the analog domain to generate a digital value that is to be processed by a digital signal processor (DSP) (26) to provide on the output a digital output. Each data node in each processing element in the DSP (26) is mirrored by the way of a corresponding data node in the mirror circuit (36). This results in the addition of noise via a noise adder (28) such that each data node in the main portion of the DSP (26) that can draw current from the power supply during a transition will have a corresponding complement node in the mirror circuit (36). Each data node in the mirror circuit will add noise via a transition drawing current from the power supply whenever the transition does not occur at the corresponding data node in the main portion of the DSP (26). Therefore, di/dt noise will be added for each cycle, regardless of the data pattern. This is effected by insuring that, for each data cycle, each data node undergoes a positive and a negative transition. By using a return-to-zero data stream, i.e., inserting a zero in each cycle at each data node, a positive transition and a negative transition can be insured during each data cycle.
摘要翻译：提供了一个Δ-Σ模拟/数字转换器，用于在模拟域中操作以产生要由数字信号处理器（DSP）（26）处理的数字值，以在输出端提供数字输出。 DSP（26）中的每个处理元件中的每个数据节点通过镜像电路（36）中对应的数据节点的方式进行镜像。这导致通过噪声加法器（28）增加噪声，使得在转换期间能够从电源抽取电流的DSP（26）的主要部分中的每个数据节点将在镜像电路中具有对应的补码节点（36）。只要在DSP（26）的主要部分中的对应数据节点处不发生转换，镜像电路中的每个数据节点将通过来自电源的转换绘制电流来增加噪声。因此，无论数据模式如何，都会为每个周期添加di / dt噪声。这通过确保对于每个数据周期，每个数据节点经历正和负转换来实现。通过使用归零数据流，即在每个数据节点的每个周期插入零，可以在每个数据周期期间保证正转移和负转移。

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