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1. 发明授权

US6057793A Digital decimation filter and method for achieving fractional data rate reduction with minimal hardware or software overhead 失效
$Digital decimation filter and method for achieving fractional data rate reduction with minimal hardware or software overhead$
公开(公告)号：US6057793A
公开(公告)日：2000-05-02
申请号：US97141
申请日：1998-06-12
申请人： Xue-Mei Gong , Tim J. Dupuis , Jinghui Lu , Korhan Titizer
发明人： Xue-Mei Gong , Tim J. Dupuis , Jinghui Lu , Korhan Titizer
IPC分类号： H03H17/04 , H03M3/00
CPC分类号： H03H17/0671
摘要： An analog-to-digital converter is provided for producing digital signal representative of analog signals. Noise induced upon the digital signals can be substantially removed using a digital decimation filter. The decimation filter includes a front-end portion which receives the digital data at a relatively high sample rate and performs filtering operations with minimal complexity. Preferably, the front-end portion includes at least one stage of filtering and more preferably at least two filter stages, each of which perform interpolation separate from decimation. According to one embodiment, the first stage of the front-end portion involves decimation and the latter stage or stages of that portion involves a combination of interpolation and decimation. The cumulative effect is to reduce the sample rate of the incoming data stream produced by, for example, a quantizer to a value which can be more easily manipulated by the back-end portion of the digital decimation filter. The front-end portion can therefore reduce the data rate change factor K to a smaller, fixed integer data rate change factor K.sub.1, regardless of whether data rate change factor K is an integer number or involves a fractional number.

2. 发明授权

US07599431B1 Combined decision feedback equalization and linear equalization 有权
标题翻译：组合决策反馈均衡和线性均衡
公开(公告)号：US07599431B1
公开(公告)日：2009-10-06
申请号：US10997159
申请日：2004-11-24
申请人： Stephen D. Anderson , Michael A. Nix , Brian T. Brunn , Jinghui Lu , David E. Tetzlaff
发明人： Stephen D. Anderson , Michael A. Nix , Brian T. Brunn , Jinghui Lu , David E. Tetzlaff
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04L25/03038 , H04L25/03057 , H04L25/03343
摘要： A communication system includes a transmitter, a communication channel, and a receiver. The transmitter includes a pre-emphasis module, a summing module, a line driver, and a decision feedback pre-emphasis (DFP) module to produce a pre-emphasized serial stream of data based on a communications channel response and an inter-symbol interference level. The receiver includes a linear equalizer, a summing module, a decision module, and a decision feedback equalization (DFE) module. The linear equalizer produces an equalized serial stream of data. The summing module sums at least one data element of the equalized serial stream of data with DFE data elements to produce equalized data elements. The decision module interprets the equalized data elements to produce interpreted data elements to DFE module, which produces the DFE data elements from the interpreted data elements.
摘要翻译：通信系统包括发射机，通信信道和接收机。发射机包括预加重模块，求和模块，线路驱动器和决策反馈预加重（DFP）模块，以基于通信信道响应和符号间干扰产生预先强调的串行数据流水平。接收机包括线性均衡器，求和模块，决策模块和判决反馈均衡（DFE）模块。线性均衡器产生均衡的串行数据流。求和模块将均衡的串行数据流中的至少一个数据元素与DFE数据元素相加以产生均衡的数据元素。决策模块解释均衡的数据元素以产生解释的数据元素到DFE模块，其从解释的数据元素产生DFE数据元素。

3. 发明授权

US6161118A Digital comb filter having a cascaded integrator stage with adjustable gain 失效
标题翻译：数字梳状滤波器具有可调增益的级联积分器级
公开(公告)号：US6161118A
公开(公告)日：2000-12-12
申请号：US96782
申请日：1998-06-12
申请人： Jinghui Lu
发明人： Jinghui Lu
IPC分类号： H03H17/06 , G06F5/00 , G06F17/10
CPC分类号： H03H17/0671
摘要： A comb filter is provided for achieving substantial attenuation of aliasing or imaging bans of a signal to be filtered. The comb filter can perform decimation or interpolation, depending upon its application. Integration can include an integration term with adjustable voltage accumulation at a particular sample point in time. The accumulation factor can be an integer or fractional number and is introduced at a sample count value L within each of M number of samples formed by the rate change switch within the comb filter. The amount of gain being introduced can possibly vary depending on the number of accumulation cycles programmed within configuration registers of the digital signal processor which carries out the comb filter functions. The programmable accumulator avoids having to implement a multiplication operation and the complexities associated therewith.
摘要翻译：提供梳状滤波器用于实现待滤波信号的混叠或成像禁令的实质衰减。梳状滤波器可以根据其应用执行抽取或插值。集成可以包括在特定采样点处具有可调电压累积的积分项。积分因子可以是整数或分数，并且在由梳状滤波器内的速率变换开关形成的M个采样的每个样本计数值L内引入。引入的增益量可以根据执行梳状滤波器功能的数字信号处理器的配置寄存器内编程的累积循环的数量而变化。可编程累加器避免必须执行乘法运算和与之相关的复杂性。

4. 发明申请

US20110096990A1 Video Codec Method and System 有权
标题翻译：视频编解码方法和系统
公开(公告)号：US20110096990A1
公开(公告)日：2011-04-28
申请号：US12605255
申请日：2009-10-23
申请人： Jinghui Lu , Song Qiu , Hao Wang
发明人： Jinghui Lu , Song Qiu , Hao Wang
IPC分类号： G06K9/34 , G06K9/36
CPC分类号： H04N19/33 , H04N19/103 , H04N19/136 , H04N19/17
摘要： Techniques pertaining to scalable video codec are disclosed. According to one aspect of the present invention, a video image is analyzed and a region of interest (ROI) and a region of non-interest (non-ROI) are identified. By comparing the non-ROI image with that of a previous image, a background ignored identifier is created indicating whether the non-ROI can be ignored during encoding and decoding processes. Based on the status of the background ignored identifier, the encoder encodes the images into a basic layer (BL) and an enhanced layer (EL), and transmits the coded bit streams along with the identifier to a decoder. The decoder reconstructs the image based on the identifier and the BL and the EL bit streams.
摘要翻译：公开了与可伸缩视频编解码器有关的技术。根据本发明的一个方面，分析视频图像，并且识别感兴趣区域（ROI）和非感兴趣区域（非ROI）。通过将非ROI图像与先前图像的非ROI图像进行比较，创建背景忽略的标识符，指示在编码和解码过程期间是否可以忽略非ROI。基于背景忽略标识符的状态，编码器将图像编码为基本层（BL）和增强层（EL），并将编码的比特流与标识符一起发送到解码器。解码器基于标识符和BL和EL比特流重构图像。

5. 发明授权

US07496155B1 Duty cycle correction of a multi-gigahertz clock signal with crossover point control 有权
标题翻译：具有交叉点控制的多吉赫兹时钟信号的占空比校正
公开(公告)号：US07496155B1
公开(公告)日：2009-02-24
申请号：US11228655
申请日：2005-09-16
申请人： Jinghui Lu , Yiqin Chen
发明人： Jinghui Lu , Yiqin Chen
IPC分类号： H04L27/00
CPC分类号： H04L25/0292 , H04L7/033
摘要： A clock recovery circuit includes a crossover adjustment circuit operable to adjust a crossover point to adjust a corresponding duty cycle. The adjustment circuit comprises a feedback adjustment combining element which is implemented as summing elements and a crossover point control clock amplifier, an operational amplifier with a resistor in place of a low pass filter at an input of the operational amplifier and feedback driver. The summing element within the feedback adjustment combining element combines input clocks with feedback signals, the crossover point control clock amplifier includes adjustment driver, the two cross coupled PMOS along with the resistor connected between them, reshape input clocks, adjust cross over point and provide output clocks with DCD corrected. A modified Miller capacitor comprising a resistor in series with a capacitor across a drain and gate of a cascode transistor pair is utilized in an output stage to adjust corner frequencies.
摘要翻译：时钟恢复电路包括可操作以调整交叉点以调整相应的占空比的交叉调整电路。调节电路包括反馈调整组合元件，其被实现为求和元件和交叉点控制时钟放大器，运算放大器具有电阻器，代替在运算放大器和反馈驱动器的输入处的低通滤波器。反馈调整组合元件中的求和元素将输入时钟与反馈信号相结合，交叉点控制时钟放大器包括调整驱动器，两个交叉耦合PMOS以及连接在它们之间的电阻，重新形成输入时钟，调整交叉点并提供输出 DCD校正时钟。一个改进的米勒电容器包括与串联晶体管对的漏极和栅极上的电容器串联的电阻器，用于输出级以调整转角频率。

6. 发明授权

US07460848B1 Differential signal strength detector 有权
标题翻译：差分信号强度检测器
公开(公告)号：US07460848B1
公开(公告)日：2008-12-02
申请号：US10955062
申请日：2004-09-29
申请人： Brian T. Brunn , Jinghui Lu
发明人： Brian T. Brunn , Jinghui Lu
IPC分类号： H04B17/00 , H03K5/153
CPC分类号： H04B17/318
摘要： A signal detection circuit includes a first signal multiplier operably coupled to square an input signal, a second signal multiplier operably coupled to square a reference signal, and a filter module operably coupled to produce a digital output representative of the input signal based on a squared input signal and a squared reference signal.
摘要翻译：信号检测电路包括可操作地耦合到平方输入信号的第一信号乘法器，可操作地耦合到平方参考信号的第二信号乘法器和可操作地耦合以产生代表输入信号的数字输出的滤波器模块，其基于平方输入信号和平方参考信号。

7. 发明授权

US06611218B1 Transmitter with multiphase data combiner for parallel to serial data conversion 有权
标题翻译：具有多相数据组合器的发射机，用于并行到串行数据转换
公开(公告)号：US06611218B1
公开(公告)日：2003-08-26
申请号：US10043771
申请日：2002-01-09
申请人： Jinghui Lu , Michael A. Nix
发明人： Jinghui Lu , Michael A. Nix
IPC分类号： H03M900
CPC分类号： H03M9/00 , H03L7/06
摘要： Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes complementary data-input transistors to expedite the data combiner's response to changes in input data.
摘要翻译：描述了高速并行到串行转换器。转换器包括具有差分电流 - 转向电路的数据组合器，其通过产生表示并行数据位的差分串行版本的互补电流信号来响应并行数据位。一个实施例包括补充数据输入晶体管，以加速数据组合器对输入数据变化的响应。

8. 发明授权

US07523215B1 Method and apparatus for configuring data transmissions within a micro-area network 有权
标题翻译：用于在微区域网络内配置数据传输的方法和装置
公开(公告)号：US07523215B1
公开(公告)日：2009-04-21
申请号：US10047195
申请日：2002-01-14
申请人： Moises E. Robinson , Shahriar Rokhsaz , Jinghui Lu
发明人： Moises E. Robinson , Shahriar Rokhsaz , Jinghui Lu
IPC分类号： G06F15/16
CPC分类号： H04L69/24
摘要： A method and apparatus for a transmitting entity within a micro-area network to establish a data transmission within the network includes processing that begins by determining the identity of a target entity within the micro-area network. The processing then continues by determining transmission characteristics of at least one communication path between the transmitting entity and target entity of the micro-area network. The processing then continues by determining a transmission convention based on the transmission characteristics. The processing then continues by providing the transmission convention to the target entity.
摘要翻译：用于在微区域网内发送实体以建立网络内的数据传输的方法和装置包括通过确定微区域网内的目标实体的身份开始的处理。然后通过确定微区域网络的发送实体和目标实体之间的至少一个通信路径的传输特性来继续处理。然后通过基于传输特性确定传输约定来继续处理。然后通过向目标实体提供传输约定来继续处理。

9. 发明授权

US07058120B1 Integrated high-speed serial-to-parallel and parallel-to-serial transceiver 有权
标题翻译：集成的高速串并行和并行到串行收发器
公开(公告)号：US07058120B1
公开(公告)日：2006-06-06
申请号：US10051222
申请日：2002-01-18
申请人： Jinghui Lu , Shahriar Rokhsaz , Stephen D. Anderson , Michael A. Nix , Ahmed Younis , Michael Ren Kent , Yvette P. Lee , Firas N. Abughazaleh , Brian T. Brunn , Moises E. Robinson , Kazi S. Hossain
发明人： Jinghui Lu , Shahriar Rokhsaz , Stephen D. Anderson , Michael A. Nix , Ahmed Younis , Michael Ren Kent , Yvette P. Lee , Firas N. Abughazaleh , Brian T. Brunn , Moises E. Robinson , Kazi S. Hossain
IPC分类号： H03K11/00 , H04L25/60 , H04L25/64
CPC分类号： H03L7/093 , H03K5/1565 , H03M9/00 , H04L7/0004 , H04L7/033 , H04W4/18
摘要： A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.
摘要翻译：收发机包括接收机部分和发射机部分。接收器部分包括时钟电路，串行到并行模块和补偿。发射机部分包括时钟电路，并行到串行模块和补偿。接收器部分和发射器部分内的补偿补偿了时钟控制电路，串行到并行模块和并行到串行模块的集成电路（IC）处理限制和/或集成电路（IC）制造限制，否则限制收发器可以传输数据的速度。

10. 发明授权

US06946849B1 Circuit for calibrating a resistance 有权
标题翻译：用于校准电阻的电路
公开(公告)号：US06946849B1
公开(公告)日：2005-09-20
申请号：US10869010
申请日：2004-06-15
申请人： Jinghui Lu
发明人： Jinghui Lu
IPC分类号： H03F1/42 , H03F3/45 , G01R35/00
CPC分类号： H03F3/45188 , H03F1/42 , H03F2200/36 , H03F2203/45418 , H03F2203/45424 , H03F2203/45638 , H03F2203/45644 , H03F2203/45702
摘要： A circuit for calibrating a resistance between a first circuit node and a second circuit node is disclosed. The circuit comprises a reference resistor connected between first and second reference nodes; a first transistor having a first current-handling terminal connected to the first reference node, a second current-handling terminal, and a first control terminal; and a second transistor having a third current-handling terminal connected to the first circuit node, a fourth current-handling terminal connected to the second circuit node, and a second control terminal connected to the first control terminal.
摘要翻译：公开了一种用于校准第一电路节点和第二电路节点之间的电阻的电路。电路包括连接在第一和第二参考节点之间的参考电阻器; 具有连接到第一参考节点的第一电流处理终端的第一晶体管，第二电流处理终端和第一控制端; 以及具有连接到第一电路节点的第三电流处理终端的第二晶体管，连接到第二电路节点的第四电流处理终端和连接到第一控制端的第二控制端。

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