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1. 发明申请

US20060072685A1 Wireless communication system with hardware-based frequency burst detection 有权
公开(公告)号：US20060072685A1
公开(公告)日：2006-04-06
申请号：US10955569
申请日：2004-09-30
申请人： Xue-Mei Gong , Jing Liang , Frederick Rush , Phillip Matthews , Gannavaram Vishakhadatta
发明人： Xue-Mei Gong , Jing Liang , Frederick Rush , Phillip Matthews , Gannavaram Vishakhadatta
IPC分类号： H04L27/06
CPC分类号： H04L27/0002 , H04B1/0028 , H04B1/40 , H04B15/02
摘要： A wireless communication system is provided that includes RF circuitry and signal processing circuitry. The signal processing circuitry includes a dedicated frequency burst (FB) search hardware circuit which exhibits relatively low noise in comparison with other digital processing circuitry, such as a DSP and MCU, within the system. The RF circuitry, dedicated FB search hardware circuit and the other digital processing circuitry can each be activated and inactivated. In one embodiment, when the RF circuitry and the dedicated FB search hardware are active, other digital processing circuitry remains inactive to avoid noise problems that could degrade reception and interfere with the FB search hardware locating the FB. Noise problems in the system are thus desirably reduced.

2. 发明授权

US08692599B2 Interpolative divider linearity enhancement techniques 有权
标题翻译：插值分频线性增强技术
公开(公告)号：US08692599B2
公开(公告)日：2014-04-08
申请号：US13592160
申请日：2012-08-22
申请人： Xue-Mei Gong , Adam B. Eldredge , Susumu Hara
发明人： Xue-Mei Gong , Adam B. Eldredge , Susumu Hara
IPC分类号： H03L7/06
CPC分类号： H03L7/1976 , H03L7/081 , H03L7/104
摘要： A flexible clock synthesizer technique includes generating a phase interpolator calibration signal to adjust a phase interpolator output signal generated by a phase interpolator of an interpolative divider. The phase interpolator is responsive to a phase interpolator control code and an output signal of a fractional-N divider of the interpolative divider. The phase interpolator calibration signal is based on an error signal indicative of a phase interpolator error. The error signal may indicate a phase relationship between a reference clock signal and a feedback clock signal of a PLL. The interpolative divider may be coupled in a feedback path of the PLL. The PLL may receive a reference clock signal and the feedback clock signal may be an adjusted phase interpolator output signal. The phase interpolator calibration signal may be a phase interpolator offset code corresponding to the phase interpolator control code or a phase interpolator gain signal.
摘要翻译：灵活的时钟合成器技术包括产生相位内插器校准信号以调整由内插分频器的相位插值器产生的相位内插器输出信号。相位插值器响应于内插分频器的分数N分频器的相位内插器控制代码和输出信号。相位内插器校准信号基于指示相位内插器误差的误差信号。误差信号可以指示PLL的参考时钟信号和反馈时钟信号之间的相位关系。内插分压器可以耦合在PLL的反馈路径中。 PLL可以接收参考时钟信号，并且反馈时钟信号可以是调整的相位内插器输出信号。相位内插器校准信号可以是与相位内插器控制代码或相位内插器增益信号相对应的相位内插器偏移代码。

3. 发明申请

US20060218417A1 Automatically switching power supply sources for a clock circuit 有权
标题翻译：自动切换时钟电路的电源
公开(公告)号：US20060218417A1
公开(公告)日：2006-09-28
申请号：US11089836
申请日：2005-03-24
申请人： Wenjung Sheng , Shyam Somayajula , Xue-Mei Gong
发明人： Wenjung Sheng , Shyam Somayajula , Xue-Mei Gong
IPC分类号： G06F1/00
CPC分类号： G06F1/04 , G06F1/263
摘要： In one embodiment, a power supply switching circuit may automatically provide power to a clock circuit from one of an auxiliary power supply and a main power supply, based on a voltage of the main power supply. To provide automatic switching, a switch circuit coupled between the power supplies and the clock circuit may be controlled by a voltage detector, in some embodiments.
摘要翻译：在一个实施例中，电源开关电路可以基于主电源的电压自动地向辅助电源和主电源之一提供电力到时钟电路。为了提供自动切换，在一些实施例中，耦合在电源和时钟电路之间的开关电路可以由电压检测器控制。

4. 发明申请

US20060214738A1 Clock circuit with programmable load capacitors 失效
标题翻译：具有可编程负载电容的时钟电路
公开(公告)号：US20060214738A1
公开(公告)日：2006-09-28
申请号：US11089857
申请日：2005-03-24
申请人： Wenjung Sheng , Shyam Somayajula , Xue-Mei Gong
发明人： Wenjung Sheng , Shyam Somayajula , Xue-Mei Gong
IPC分类号： H03B5/12
CPC分类号： H03K3/0307 , H03B5/36 , H03B2201/0266 , H03K3/012
摘要： In one embodiment, the present invention includes methods and apparatus for providing initial control values to programmable load capacitors of an oscillator, such as that of a real time clock circuit. Using the initial values, the real time clock circuit may begin operation, enabling additional circuitry within an integrated circuit to begin operation. This additional circuitry may cause operating values to program the load capacitors to provide a desired reference clock based on a given system's requirements.
摘要翻译：在一个实施例中，本发明包括用于向诸如实时时钟电路的振荡器的可编程负载电容器提供初始控制值的方法和装置。使用初始值，实时时钟电路可以开始运行，使集成电路中的附加电路能够开始运行。这个额外的电路可以使操作值对负载电容器进行编程，以根据给定的系统要求提供所需的参考时钟。

5. 发明授权

US06266002B1 2nd order noise shaping dynamic element matching for multibit data converters 有权
标题翻译：多位数据转换器的二阶噪声整形动态元件匹配
公开(公告)号：US06266002B1
公开(公告)日：2001-07-24
申请号：US09394145
申请日：1999-09-10
申请人： Xue-Mei Gong , Eric Gaalaas , Mark Alexander
发明人： Xue-Mei Gong , Eric Gaalaas , Mark Alexander
IPC分类号： H03M166
CPC分类号： H03M1/0668 , H03M1/74 , H03M3/464 , H03M3/502
摘要： A multi-bit DAC (109) is provided as part of a digital-to-analog data converter (DAC). The multi-bit DAC is comprised of a plurality of single-bit DACs (503) which have the values thereof selected through a digital encoder (505). The digital encoder (505) performs dynamic element matching (DEM) on an input data value. The sequence of selection is performed such that the element mismatch noise response of the DAC (109) is shaped. The outputs are summed at a summing junction (507) and then filtered with a low pass filter (113). In the noise shaping response, a cyclical second order response is provided with a Data Weighted Averaging (DWA) technique wherein the outputs of the DACs are restricted to one of two states. To achieve this, select ones of the output values are changed in order to comply with this restriction, thus deviating from a uniform element selection algorithm. This provides a constrained second order response which accounts for mismatching of the DAC elements (503).
摘要翻译：提供多位DAC（109）作为数模转换器（DAC）的一部分。多位DAC由多个通过数字编码器（505）选择的值的单位DAC（503）组成。数字编码器（505）对输入数据值执行动态元素匹配（DEM）。执行选择的顺序，使得DAC（109）的元件失配噪声响应成形。输出在加法结（507）相加，然后用低通滤波器（113）滤波。在噪声整形响应中，循环二阶响应具有数据加权平均（DWA）技术，其中DAC的输出被限制为两种状态中的一种状态。为了实现这一点，选择一个输出值被改变以符合该限制，从而偏离均匀的元素选择算法。这提供了限制的二阶响应，其考虑到DAC元件（503）的不匹配。

6. 发明授权

US6011501A Circuits, systems and methods for processing data in a one-bit format 失效
标题翻译：用于以一位格式处理数据的电路，系统和方法
公开(公告)号：US6011501A
公开(公告)日：2000-01-04
申请号：US224389
申请日：1998-12-31
申请人： Xue-Mei Gong , John James Paulos , Mark Alexander , Eric Gaalaas , Dylan Hester
发明人： Xue-Mei Gong , John James Paulos , Mark Alexander , Eric Gaalaas , Dylan Hester
IPC分类号： H03M1/66 , H03H19/00 , H03M1/06 , H03M3/02 , H03M3/04
CPC分类号： H03M3/504 , H03M1/066 , H03M3/346 , H03M3/392 , H03M3/502
摘要： Digital-to-analog conversion circuitry 100 is shown including a path for processing data in a 1-bit format. First portion of an analog finite impulse response filter 300 includes pre-selected number of delay elements 301 for receiving stream of data in the 1-bit format and outputting a plurality of signals in response. A switched capacitor digital-to-analog converter 106 forms a second portion of the finite impulse response filter 301 and has a plurality of elements each receiving one of the plurality of signals as selected to effectuate a set of filter coefficients, converter 106 summing the plurality of signals and outputting an analog data stream.
摘要翻译：示出了数模转换电路100，其包括用于以1位格式处理数据的路径。模拟有限脉冲响应滤波器300的第一部分包括用于接收1比特格式的数据流的预选数量的延迟元件301，并且响应地输出多个信号。开关电容器数模转换器106形成有限脉冲响应滤波器301的第二部分，并且具有多个元件，每个元件接收所选择的多个信号中的一个以实现一组滤波器系数，转换器106将多个的信号并输出模拟数据流。

7. 发明授权

US08671286B2 Automatically switching power supply sources for a clock circuit 有权
标题翻译：自动切换时钟电路的电源
公开(公告)号：US08671286B2
公开(公告)日：2014-03-11
申请号：US12079565
申请日：2008-03-27
申请人： Wenjung Sheng , Shyam S. Somayajula , Xue-Mei Gong
发明人： Wenjung Sheng , Shyam S. Somayajula , Xue-Mei Gong
IPC分类号： G06F1/26
CPC分类号： G06F1/04 , G06F1/263
摘要： In one embodiment, a power supply switching circuit may automatically provide power to a clock circuit from one of an auxiliary power supply and a main power supply, based on a voltage of the main power supply. To provide automatic switching, a switch circuit coupled between the power supplies and the clock circuit may be controlled by a voltage detector, in some embodiments.
摘要翻译：在一个实施例中，电源开关电路可以基于主电源的电压自动地向辅助电源和主电源之一提供电力到时钟电路。为了提供自动切换，在一些实施例中，耦合在电源和时钟电路之间的开关电路可以由电压检测器控制。

8. 发明申请

US20130300467A1 HIGHER-ORDER PHASE NOISE MODULATOR TO REDUCE SPURS AND QUANTIZATION NOISE 有权
标题翻译：更高阶段噪声调节器，以减少火花和量化噪音
公开(公告)号：US20130300467A1
公开(公告)日：2013-11-14
申请号：US13469936
申请日：2012-05-11
申请人： Adam B. Eldredge , Xue-Mei Gong
发明人： Adam B. Eldredge , Xue-Mei Gong
IPC分类号： H03L7/08
CPC分类号： H03L7/08 , H03L7/081 , H03L7/1976 , H03M7/3022 , H03M7/3026 , H03M7/3037 , H03M7/304 , H03M7/3042
摘要： A frequency synthesizer capable of generating a clock signal having reduced digital spurs and reduced jitter is described. An apparatus includes a frequency modulator configured to generate a divide control signal and a digital quantization error signal in response to a divide ratio. The apparatus includes a phase modulator configured to generate a phase error signal based on the digital quantization error signal. The phase modulator is an n-order sigma-delta modulator module, n being an integer greater than one. The apparatus may include an interpolative divider configured to generate a feedback signal in a phase-locked loop (PLL) based on an output signal of the PLL, the divide control signal, and the phase error signal. The interpolative divider may include the frequency modulator and the phase modulator. The phase modulator may have a unity gain signal transfer function.
摘要翻译：描述了一种频率合成器，其能够产生具有减少的数字杂散和减少的抖动的时钟信号。一种装置包括：频率调制器，被配置为响应于分频比产生除法控制信号和数字量化误差信号。该装置包括：相位调制器，被配置为基于数字量化误差信号产生相位误差信号。相位调制器是n阶Σ-Δ调制器模块，n是大于1的整数。该装置可以包括内插分配器，其经配置以基于PLL的输出信号，分频控制信号和相位误差信号在锁相环（PLL）中产生反馈信号。内插分频器可以包括频率调制器和相位调制器。相位调制器可以具有单位增益信号传递函数。

9. 发明授权

US07593482B2 Wireless communication system with hardware-based frequency burst detection 有权
标题翻译：无线通信系统具有基于硬件的频率突发检测
公开(公告)号：US07593482B2
公开(公告)日：2009-09-22
申请号：US10955569
申请日：2004-09-30
申请人： Xue-Mei Gong , Jing Liang , Frederick A. Rush , Phillip M. Matthews , Gannavaram Diwakar Vishakhadatta
发明人： Xue-Mei Gong , Jing Liang , Frederick A. Rush , Phillip M. Matthews , Gannavaram Diwakar Vishakhadatta
IPC分类号： H03K9/00
CPC分类号： H04L27/0002 , H04B1/0028 , H04B1/40 , H04B15/02
摘要： A wireless communication system is provided that includes RF circuitry and signal processing circuitry. The signal processing circuitry includes a dedicated frequency burst (FB) search hardware circuit which exhibits relatively low noise in comparison with other digital processing circuitry, such as a DSP and MCU, within the system. The RF circuitry, dedicated FB search hardware circuit and the other digital processing circuitry can each be activated and inactivated. In one embodiment, when the RF circuitry and the dedicated FB search hardware are active, other digital processing circuitry remains inactive to avoid noise problems that could degrade reception and interfere with the FB search hardware locating the FB. Noise problems in the system are thus desirably reduced.
摘要翻译：提供了一种包括RF电路和信号处理电路的无线通信系统。信号处理电路包括与系统内的其它数字处理电路（例如DSP和MCU）相比显示相对低的噪声的专用频率突发（FB）搜索硬件电路。 RF电路，专用FB搜索硬件电路和其他数字处理电路可以各自被激活和停用。在一个实施例中，当RF电路和专用FB搜索硬件有效时，其他数字处理电路保持不活动，以避免可能降低接收的干扰问题，并干扰定位FB的FB搜索硬件。因此，希望减少系统中的噪声问题。

10. 发明授权

US08994420B2 Higher-order phase noise modulator to reduce spurs and quantization noise 有权
标题翻译：高阶相位噪声调制器可减少杂散和量化噪声
公开(公告)号：US08994420B2
公开(公告)日：2015-03-31
申请号：US13469936
申请日：2012-05-11
申请人： Adam B. Eldredge , Xue-Mei Gong
发明人： Adam B. Eldredge , Xue-Mei Gong
IPC分类号： H03L7/06 , H03L7/08
CPC分类号： H03L7/08 , H03L7/081 , H03L7/1976 , H03M7/3022 , H03M7/3026 , H03M7/3037 , H03M7/304 , H03M7/3042
摘要： A frequency synthesizer capable of generating a clock signal having reduced digital spurs and reduced jitter is described. An apparatus includes a frequency modulator configured to generate a divide control signal and a digital quantization error signal in response to a divide ratio. The apparatus includes a phase modulator configured to generate a phase error signal based on the digital quantization error signal. The phase modulator is an n-order sigma-delta modulator module, n being an integer greater than one. The apparatus may include an interpolative divider configured to generate a feedback signal in a phase-locked loop (PLL) based on an output signal of the PLL, the divide control signal, and the phase error signal. The interpolative divider may include the frequency modulator and the phase modulator. The phase modulator may have a unity gain signal transfer function.
摘要翻译：描述了一种频率合成器，其能够产生具有减少的数字杂散和减少的抖动的时钟信号。一种装置包括：频率调制器，被配置为响应于分频比产生除法控制信号和数字量化误差信号。该装置包括：相位调制器，被配置为基于数字量化误差信号产生相位误差信号。相位调制器是n阶Σ-Δ调制器模块，n是大于1的整数。该装置可以包括内插分配器，其经配置以基于PLL的输出信号，分频控制信号和相位误差信号在锁相环（PLL）中产生反馈信号。内插分频器可以包括频率调制器和相位调制器。相位调制器可以具有单位增益信号传递函数。

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