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1. 发明授权

US5696708A Digital filter with decimated frequency response 失效
标题翻译：具有抽取频率响应的数字滤波器
公开(公告)号：US5696708A
公开(公告)日：1997-12-09
申请号：US413356
申请日：1995-03-30
申请人： Ka Yin Leung
发明人： Ka Yin Leung
IPC分类号： G06F17/17
CPC分类号： G06F17/17
摘要： A method for changing the frequency of a low-pass Finite Impulse Response (FIR) filter with a fixed frequency clock utilizes a decimation-by-coefficient technique. The decimation-by-coefficient method utilizes a single set of coefficients that are stored in a coefficient Read Only Memory (ROM) (64). Data is input to an elastic buffer (60) with multiplications performed by a multiplication circuit (62). To realize a low frequency filter, all coefficients are utilized in the multiplication operations with sequential multiplies. These are accumulated in register (70), this providing a high precision filter. To increase frequency by a factor of two--to decimate the coefficients by a factor of two, it is only necessary to utilize every other coefficient, such that only a single fixed clock (78) is required.
摘要翻译：用固定频率时钟改变低通有限脉冲响应（FIR）滤波器的频率的方法利用抽取系数技术。抽取系数法利用存储在系数只读存储器（ROM）（64）中的单组系数。通过乘法电路（62）执行的乘法将数据输入到弹性缓冲器（60）。为了实现低频滤波器，所有系数都用于具有顺序乘法的乘法运算。这些都在寄存器（70）中累积，这提供了一个高精度的滤波器。为了将频率提高2倍，将系数抽取2倍，仅需要利用每个其他系数，使得仅需要单个固定时钟（78）。

2. 发明授权

US06271780B1 Gain ranging analog-to-digital converter with error correction 有权
标题翻译：增益范围模数转换器，具有纠错功能
公开(公告)号：US06271780B1
公开(公告)日：2001-08-07
申请号：US09168601
申请日：1998-10-08
申请人： Xue-Mei Gong , Ka Yin Leung , Eric J. Swanson
发明人： Xue-Mei Gong , Ka Yin Leung , Eric J. Swanson
IPC分类号： H03H188
CPC分类号： H03M3/488 , H04R3/00
摘要： A gain ranging AD converter is provided having two separate gain paths. There is provided a low-gain path and a high-gain path. The low gain path is processed through an analog modulator (333) and then through a filter section to provide on an output of a high-pass filter (339), a low-gain signal which is then compensated for in an equalizer section (347). This equalizing section (347) calibrates the output signal to ensure that the difference between the calibrated signal and the high-gain signal differs only by the fixed gain between the two paths. The high-gain path also includes a modulator (335) for processing through a filter section to provide on the output of a high-pass filter section (343) a high-gain signal. A calibration generator (361) is utilized to generate the parameters for performing the equalization. This calibration generator (361) utilizes both phase and amplitude information from the high-gain path and from both the calibrated low-gain path to generate the calibration parameters for use by the equalizing section (347). Thereafter, the mixing operation is performed to provide a “blend” before summing with a summing junction (351).
摘要翻译：增益测距AD转换器具有两个独立的增益路径。提供了低增益路径和高增益路径。通过模拟调制器（333）处理低增益路径，然后通过滤波器部分提供高通滤波器（339）的输出，然后在均衡器部分（347）中对低增益信号进行补偿）。该均衡部分（347）校准输出信号，以确保校准信号和高增益信号之间的差异仅仅在两条路径之间的固定增益之间不同。高增益路径还包括用于通过滤波器部分处理以在高通滤波器部分（343）的输出上提供高增益信号的调制器（335）。校准发生器（361）用于产生用于执行均衡的参数。该校准发生器（361）利用来自高增益路径的相位和幅度信息以及来自校准的低增益路径的两个相位和幅度信息来生成用于均衡部分（347）的校准参数。此后，执行混合操作以在与求和结（351）相加之前提供“混合”。

3. 发明授权

US5748040A Fully differential high gain cascode amplifier 失效
标题翻译：全差分高增益共源共栅放大器
公开(公告)号：US5748040A
公开(公告)日：1998-05-05
申请号：US749383
申请日：1996-11-06
申请人： Ka Yin Leung
发明人： Ka Yin Leung
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F3/45659 , H03F2203/45356 , H03F2203/45682
摘要： A very high gain cascode amplifier includes a cascoded differential structure wherein a cascoded N-channel leg comprised of two series connected transistors (56) and (58) are connected between an output node (30) and ground with a corresponding P-channel cascode leg comprised of series connected P-channel transistors (38) and (40) connected between node (30) and V.sub.DD. Transistor (58) is connected to bias voltage, with transistor (56) having a gate thereof connected to a bias circuit (72) which provides gain thereto to increase the gain of a cascoded leg while not introducing any error into the amplifier. The bias circuit (72) has an imbedded structure that sets the gate voltage of transistor (56) to a voltage equal to one threshold voltage plus twice the V.sub.on voltage of transistors (56) and (58). This is achieved via negative feedback with transistors that track any errors, such that all errors are cancelled out and the maximum voltage swing is maintained for all operational characteristics of the cascoded leg.
摘要翻译：非常高的增益共源共栅放大器包括级联差分结构，其中由两个串联连接的晶体管（56）和（58）组成的级联N沟道支路连接在输出节点（30）和地之间，并与相应的P沟道共源共享支路包括连接在节点（30）和VDD之间的串联连接的P沟道晶体管（38）和（40）。晶体管（58）连接到偏置电压，晶体管（56）的栅极连接到偏置电路（72），偏置电路（72）提供增益，以增加级联支路的增益，同时不向放大器引入任何误差。偏置电路（72）具有嵌入式结构，其将晶体管（56）的栅极电压设置为等于一个阈值电压加上晶体管（56）和（58）的Von电压的两倍的电压。这是通过负反馈来实现的，晶体管跟踪任何误差，使得所有误差被抵消，并且对于共享的腿的所有操作特性都保持最大电压摆幅。

4. 发明授权

US5652585A Multiple function analog-to-digital converter with multiple serial outputs 失效
标题翻译：具有多个串行输出的多功能模数转换器
公开(公告)号：US5652585A
公开(公告)日：1997-07-29
申请号：US416618
申请日：1995-04-05
申请人： Ka Yin Leung , Kafai Leung , Eric J. Swanson
发明人： Ka Yin Leung , Kafai Leung , Eric J. Swanson
IPC分类号： H03H17/02 , H03M3/02 , H03M3/04 , H03M7/00 , H03M1/12
CPC分类号： H03M7/3008 , H03H17/0286 , H03M3/462 , H03M7/3026 , H03M7/3042
摘要： An analog-to-digital converter is comprised of an analog delta-sigma modulator (10) and a digital processing section (14). The digital processing section (14) is comprised of a plurality of digital processing sections fabricated on a monolithic device. A high precision FIR filter (20) is provided for providing a high resolution output on a bus (22). Additionally, a low group delay FIR filter (30) is provided to filter the data and provide an output with a much lower delay than that of the FIR filter (20). The output of filter (20) can either be processed through a high-pass filter (40) and/or through a noise shaping psycho-acoustic filter (36) to provide select outputs. These outputs are all input to the serial interface device (52), which is operable to select one of the outputs, that of the filter (30), that of the filter (20), or that of the output of the noise shaping filter (36) or that of the filter (40) for conversion to a serial data stream. Two serial data streams can be generated at the same time from different ones of the inputs. Configuration data can be input to various configuration registers through a data input port (58), this allowing selection of the different functions during the operation thereof.
摘要翻译：模拟 - 数字转换器由模拟Δ-Σ调制器（10）和数字处理部分（14）组成。数字处理部分（14）由在单片装置上制造的多个数字处理部分组成。提供了一种用于在总线（22）上提供高分辨率输出的高精度FIR滤波器（20）。此外，提供低群延迟FIR滤波器（30）以对数据进行滤波并提供具有比FIR滤波器（20）的延迟低得多的延迟的输出。滤波器（20）的输出可以通过高通滤波器（40）和/或通过噪声整形心理声学滤波器（36）进行处理，以提供选择输出。这些输出全部输入到串行接口设备（52），其可操作以选择滤波器（30），滤波器（20）的输出，噪声整形滤波器（20）的输出（36）或滤波器（40）的输出端转换为串行数据流。可以从不同的输入端同时生成两个串行数据流。配置数据可以通过数据输入端口（58）输入到各种配置寄存器，这允许在其操作期间选择不同的功能。

5. 发明授权

US5777912A Linear phase finite impulse response filter with pre-addition 失效
标题翻译：具有预加法的线性相位有限脉冲响应滤波器
公开(公告)号：US5777912A
公开(公告)日：1998-07-07
申请号：US623134
申请日：1996-03-28
申请人： Ka Yin Leung , Eric J. Swanson , Kafai Leung
发明人： Ka Yin Leung , Eric J. Swanson , Kafai Leung
IPC分类号： H03H17/06 , G06F17/10
CPC分类号： H03H17/06
摘要： A linear phase FIR filter includes a multiplication/accumulator engine which is operable to receive the multi-level data stream and multiply it by predetermined filter coefficients. The coefficients are symmetrical to allow a pre-addition operation wherein the data is first stored in a buffer and then the data for symmetrical coefficients added before multiplication by the coefficient. This results in a reduction of multiplications by a factor of two, thus allowing the multiplication/accumulator engine to operate at one-half the clock rate of the oversampled multi-level data bit stream. The pre-addition operation results in values of greater than "1" and less than "-1" which are then converted in the multiplication/accumulator engine to restrict the values that are input to the multiplication/accumulator engine to values of "+1", "0" and "-1", to allow the multiplication/accumulator engine to only perform a "pass through" of the coefficient value, an "inversion" of the coefficient value or replace the coefficient value with a "null" value. This is facilitated by processing the tri-level data through two paths, one for the "-1" and one for the "-1" term and providing a common mode offset in each of the paths. Additionally, the "-1" term has a correction factor associated therewith that can be added in the "-1" path prior to summing the two terms to provide a digital output at the sampling frequency.
摘要翻译：线性相位FIR滤波器包括乘法/累加器引擎，其可操作以接收多电平数据流并将其乘以预定的滤波器系数。系数是对称的，以允许预先加法操作，其中首先将数据存储在缓冲器中，然后将数据乘以系数之前加上的对称系数。这导致乘法减少2倍，从而允许乘法/累加器引擎以过采样多电平数据比特流的时钟速率的一半工作。预加法运算导致大于“1”且小于“-1”的值，然后在乘法/累加器引擎中转换，将输入乘法/累加器引擎的值限制为“+1” “，”0“和”-1“，以允许乘法/累加器引擎仅执行系数值的”通过“，系数值的”反转“或者以”零“值代替系数值。这通过两个路径处理三电平数据来实现，一个用于“-1”，一个用于“-1”项，并且在每个路径中提供共模偏移。此外，“-1”项具有与之相关联的校正因子，其可以在对两个项求和之前以“-1”路径相加，以提供采样频率处的数字输出。

6. 发明授权

US06356872B1 Method and apparatus for storing digital audio and playback thereof 失效
标题翻译：用于存储数字音频及其回放的方法和装置
公开(公告)号：US06356872B1
公开(公告)日：2002-03-12
申请号：US08719986
申请日：1996-09-25
申请人： Ka Yin Leung , Eric J. Swanson , Kafai Leung
发明人： Ka Yin Leung , Eric J. Swanson , Kafai Leung
IPC分类号： G10L2100
CPC分类号： G10L21/0364
摘要： A data conversion device is provided for storing digital data in a DAT (332) at a 16-bit word length and then recovering the data at a 24-bit word length with an overall reduction in truncation noise that would be inherently associated with data at the 16-bit word length. This is facilitated by noise shaping the data at the 16-bit word length prior to storage in the DAT (332) with a noise-shaping filter (324). This results in truncation noise in the lower portion of the frequency band being shifted to the higher portion of the band. When the data is recovered, it is converted to a 24-bit word length and then processed through a bandpass filter to filter out the higher frequency noise to yield a signal that has a maximum noise equal to or less than that in the lower portion of the band stored in the DAT (332). Since the truncation noise was shifted from the lower band to the upper band, this is a lower noise level than that inherently associated with the 16-bit word length.
摘要翻译：提供了一种数据转换装置，用于以16位字长将数字数据存储在DAT（332）中，然后以24位字长恢复数据，同时全局减少截断噪声，该截断噪声本质上与 16位字长。这通过在使用噪声整形滤波器（324）存储在DAT（332）中之前对16位字长的数据进行噪声整形来促进。这导致频带下部的截断噪声转移到频带的较高部分。当数据被恢复时，将其转换为24位字长，然后通过带通滤波器进行处理，以滤除更高频率的噪声，以产生最大噪声等于或小于存储在DAT（332）中的乐队。由于截断噪声从较低频带偏移到较高频带，因此与16位字长固有相关的噪声水平较低。

7. 发明授权

US5719573A Analog modulator for A/D converter utilizing leap-frog filter 失效
标题翻译：用于A / D转换器的模拟调制器利用跳跃式滤波器
公开(公告)号：US5719573A
公开(公告)日：1998-02-17
申请号：US457870
申请日：1995-06-01
申请人： Ka Yin Leung , Eric J. Swanson
发明人： Ka Yin Leung , Eric J. Swanson
IPC分类号： H03H19/00 , H03M3/02 , H03M3/00
CPC分类号： H03M3/448 , H03H19/004 , H03M3/43 , H03M3/452
摘要： An analog modulator is provided having seven switched-capacitor integrators (62)-(74) disposed in a leap-frog filter configuration with a plurality of feedback taps (76)-(88) provided from the output to each of the integrators (62)-(74). These are summed in a summation junction (90), the output thereof input to a quantizing circuit (92) for input back to a summation junction alter a D to A circuit (60) for summation with the analog input signal and then input to the first integrator (62). The first feedback structures (98)-(102) are provided for connection between the output of the last of the integrated structures (74) and the input of the preceding one thereof such that the feedback structure (98) is connected across integrators (64) and integrator (66), feedback structure (100) connected between integrators (68)-(70) and integrator (102) connected against integrators (72) and (74). Leap-frog feedback elements are connected across integrators (70) and (72) and leap-frog feedback filter (104) is connected across integrator (66) and (68).
摘要翻译：提供了一种模拟调制器，具有七个开关电容积分器（62） - （74），其布置在跨越滤波器配置中，具有从输出到每个积分器（62）提供的多个反馈抽头（76） - （88）） - （74）。这些在加法结（90）中相加，其输出被输入到量化电路（92），用于输入到加法结，改变D到A电路（60）以与模拟输入信号相加，然后输入到第一积分器（62）。第一反馈结构（98） - （102）被提供用于在最后一个集成结构（74）的输出和其前一个的输入之间连接，使得反馈结构（98）跨越积分器（64 ）和积分器（66），连接在与积分器（72）和（74）连接的积分器（68） - （70）和积分器（102）之间的反馈结构（100）。跨越反馈元件跨越积分器（70）和（72）连接，并且跨越积分器（66）和（68）的跨越式反馈滤波器（104）连接。

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