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11. 发明申请

US20120289018A1 SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR 有权
标题翻译： SOI SiGe-BASE横向双极晶体管晶体管
公开(公告)号：US20120289018A1
公开(公告)日：2012-11-15
申请号：US13556372
申请日：2012-07-24
申请人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
发明人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
IPC分类号： H01L21/331
CPC分类号： H01L29/7317 , H01L27/0821 , H01L27/1203 , H01L29/0808 , H01L29/165 , H01L29/66265
摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。基底还可以包括上硅基区和/或下硅基区。在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

12. 发明申请

US20120190192A1 Metal-Semiconductor Intermixed Regions 有权
公开(公告)号：US20120190192A1
公开(公告)日：2012-07-26
申请号：US13012043
申请日：2011-01-24
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/44
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

13. 发明申请

US20120112246A1 DEVICES HAVING REDUCED SUSCEPTIBILITY TO SOFT-ERROR EFFECTS AND METHOD FOR FABRICATION 有权
标题翻译：具有降低对软错误效应的可靠性的装置和制造方法
公开(公告)号：US20120112246A1
公开(公告)日：2012-05-10
申请号：US12939506
申请日：2010-11-04
申请人： TAK H. NING , Philip J. Oldiges
发明人： TAK H. NING , Philip J. Oldiges
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878
摘要： A semiconductor-on-insulator (SOI) substrate complementary metal oxide semiconductor (CMOS) device and fabrication methods include a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). Each of the PFET and the NFET include a transistor body of a first type of material and source and drain regions. The source and drain regions have a second type of material such that an injection charge into the source and drain region is greater than a parasitic charge into the transistor body to decrease parasitic bipolar current gain, increase critical charge (Qcrit) and reduce sensitivity to soft errors.
摘要翻译：绝缘体上半导体（SOI）衬底互补金属氧化物半导体（CMOS）器件和制造方法包括p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 PFET和NFET中的每一个包括第一类材料和源极和漏极区的晶体管体。源极和漏极区域具有第二类型的材料，使得源极和漏极区域中的注入电荷大于晶体管本体中的寄生电荷以降低寄生双极性电流增益，增加临界电荷（Qcrit）并降低对软件的灵敏度错误。

14. 发明授权

US08063424B2 Embedded photodetector apparatus in a 3D CMOS chip stack 有权
标题翻译： 3D CMOS芯片堆叠中的嵌入式光电探测器
公开(公告)号：US08063424B2
公开(公告)日：2011-11-22
申请号：US12618895
申请日：2009-11-16
申请人： Fadi H. Gebara , Tak H. Ning , Qiqing C. Ouyang , Jeremy D. Schaub
发明人： Fadi H. Gebara , Tak H. Ning , Qiqing C. Ouyang , Jeremy D. Schaub
IPC分类号： H01L31/062
CPC分类号： H01L27/14634 , H01L21/743 , H01L23/481 , H01L27/1203 , H01L27/14636 , H01L27/14647 , H01L27/1469 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181
摘要： An embedded photodetector apparatus for a three-dimensional complementary metal oxide semiconductor (CMOS) stacked chip assembly having a CMOS chip and one or more thinned CMOS layers is provided. At least one of the one or more thinned CMOS layers includes an active photodiode area defined within the one or more thinned CMOS layers, the active photodiode area being receptive of an optical signal incident thereon, and the active photodiode area comprising a bulk substrate portion of the thinned CMOS layer. The bulk substrate portion has a diode photodetector formed therein.
摘要翻译：提供了一种用于具有CMOS芯片和一个或多个薄化CMOS层的三维互补金属氧化物半导体（CMOS）堆叠芯片组件的嵌入式光电检测器装置。一个或多个变薄的CMOS层中的至少一个包括限定在一个或多个变薄的CMOS层内的有源光电二极管区域，有源光电二极管区域接收入射到其上的光信号，并且有源光电二极管区域包括减薄的CMOS层。体基板部分具有形成在其中的二极管光电检测器。

15. 发明申请

US20110088008A1 METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HARDENED PROCESSOR AND RESULTING PROCESSOR 审中-公开
标题翻译：将商业微处理器转换为辐射加工处理器和结果处理器的方法
公开(公告)号：US20110088008A1
公开(公告)日：2011-04-14
申请号：US12579159
申请日：2009-10-14
申请人： John A. FIFIELD , Mark C. HAKEY , Jason D. HIBBELER , James S. NAKOS , Tak H. NING , Kenneth P. RODBELL , Ronald D. ROSE , Henry H.K. TANG , Larry WISSEL
发明人： John A. FIFIELD , Mark C. HAKEY , Jason D. HIBBELER , James S. NAKOS , Tak H. NING , Kenneth P. RODBELL , Ronald D. ROSE , Henry H.K. TANG , Larry WISSEL
IPC分类号： G06F17/50 , H03M13/05 , G06F11/10
CPC分类号： G06F17/5068 , G06F11/1048 , G06F17/505
摘要： A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.
摘要翻译：提供了一种将商业微处理器转换为辐射硬化处理器的方法，更具体地，提供了一种方法，以便以最小的技术，设计，设备和工艺基础的改变来修改用于辐射硬化应用的商业微处理器，以便于这种辐射硬化应用的快速过渡。该方法在计算基础设施中实现，并且包括评估现有商业设计的一个或多个组件将受到单个事件不适（SEU）的影响的概率。该方法还包括用免疫SEU的成分替换一个或多个成分以产生最终的装置。

16. 发明授权

US07888959B2 Apparatus and method for hardening latches in SOI CMOS devices 有权
标题翻译：用于硬化SOI CMOS器件中的锁存器的装置和方法
公开(公告)号：US07888959B2
公开(公告)日：2011-02-15
申请号：US11857596
申请日：2007-09-19
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

17. 发明申请

US20110033952A1 Sensor for Biomolecules 有权
标题翻译：生物分子传感器
公开(公告)号：US20110033952A1
公开(公告)日：2011-02-10
申请号：US12537063
申请日：2009-08-06
申请人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
发明人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
IPC分类号： G01N33/543 , H01L29/78
CPC分类号： G01N33/54373 , B82Y10/00 , G01N27/3276 , G01N27/4145 , G01N33/543 , H01L29/785 , Y10S977/721 , Y10S977/92 , Y10S977/953
摘要： A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies.
摘要翻译：用于生物分子的传感器包括包含未掺杂硅的硅片; 与硅鳍片相邻的源极区域，源极区域包括重掺杂的硅; 与所述硅鳍片相邻的漏极区域，所述漏极区域包括掺杂类型的与所述源极区域相同的掺杂类型的重掺杂硅; 以及覆盖源极区域和漏极区域之间的硅鳍片的外部部分的栅极电介质层，所述栅极电介质包括多个抗体，所述多个抗体被配置为与所述生物分子结合，使得漏极电流流动当生物分子与抗体结合时，在源区和漏区之间变化。

18. 发明申请

US20090256204A1 SOI TRANSISTOR WITH MERGED LATERAL BIPOLAR TRANSISTOR 失效
标题翻译：具有合并侧向双极晶体管的SOI晶体管
公开(公告)号：US20090256204A1
公开(公告)日：2009-10-15
申请号：US12099879
申请日：2008-04-09
申请人： Jin Cai , Jeffrey B. Johnson , Tak H. Ning , Robert R. Robison
发明人： Jin Cai , Jeffrey B. Johnson , Tak H. Ning , Robert R. Robison
IPC分类号： H01L29/786
CPC分类号： H01L29/78612 , H01L21/84 , H01L27/0722
摘要： A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.
摘要翻译：绝缘体上半导体晶体管器件包括源极区，漏极区，体区和源极横向双极晶体管。源区具有第一导电类型。体区具有第二导电类型并且位于源区和漏区之间。源极横向双极晶体管包括基极，集电极和发射极。硅化物区将基底连接到收集器。发射器是身体区域。集电体具有第二导电类型，基极是源极区，位于发射极和集电极之间。

19. 发明申请

US20090114971A1 CMOS EPROM AND EEPROM DEVICES AND PROGRAMMABLE CMOS INVERTERS 有权
标题翻译： CMOS EPROM和EEPROM器件和可编程CMOS逆变器
公开(公告)号：US20090114971A1
公开(公告)日：2009-05-07
申请号：US11935143
申请日：2007-11-05
申请人： Jin Cai , Tak H. Ning , John M. Safran
发明人： Jin Cai , Tak H. Ning , John M. Safran
IPC分类号： H01L27/092 , H01L27/12
CPC分类号： H01L21/823857 , G11C16/0433 , G11C16/10 , H01L21/823885 , H01L21/84 , H01L27/0922 , H01L27/105 , H01L27/11521 , H01L27/11524 , H01L27/11558 , H01L27/1203 , H01L29/66825 , H01L29/785 , H01L29/7881
摘要： A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thicker than the thin gate dielectric layer. A common drain node connected both FET devices has no external connection in the case of a memory device and has an external connection in the case of an inverter. There are external circuit connections to the source regions of both FET devices and to the gate electrode of the nFET device. The pFET and nFET devices can be planar, vertical or FinFET devices.
摘要翻译： CMOS EPROM，EEPROM或逆变器装置包括具有薄栅介质层的nFET器件和与nFET器件并置的pFET器件，其具有厚栅极介电层和浮栅电极。厚栅极电介质层基本上比薄栅极电介质层厚。连接两个FET器件的公共漏极节点在存储器件的情况下没有外部连接，并且在逆变器的情况下具有外部连接。存在与FET器件的源极区域和nFET器件的栅电极的外部电路连接。 pFET和nFET器件可以是平面，垂直或FinFET器件。

20. 发明申请

US20090072313A1 HARDENED TRANSISTORS IN SOI DEVICES 审中-公开
标题翻译： SOI器件中的硬化晶体管
公开(公告)号：US20090072313A1
公开(公告)日：2009-03-19
申请号：US11857569
申请日：2007-09-19
申请人： Jin Cai , Wilfried E. Haensch , Tak H. Ning , Philip J. Oldiges , Ghavam G. Shahidi
发明人： Jin Cai , Wilfried E. Haensch , Tak H. Ning , Philip J. Oldiges , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823425 , H01L21/84 , H01L27/07 , H01L29/785 , H01L29/78612
摘要： A series transistor device includes a series source, a series drain, a first constituent transistor, and a second constituent transistor. The first constituent transistor has a first source and a first drain, and the second constituent transistor has a second source and a second drain. All of the constituent transistors have a same conductivity type. The series source is the first source, and the series drain is the second drain. A drain of one of the constituent transistors is merged with a source of another of the constituent transistors.
摘要翻译：串联晶体管器件包括串联源极，串联漏极，第一构成晶体管和第二构成晶体管。第一构成晶体管具有第一源极和第一漏极，并且第二构成晶体管具有第二源极和第二漏极。所有构成晶体管都具有相同的导电类型。串联源是第一个源，串联漏极是第二个漏极。一个构成晶体管的漏极与另一个构成晶体管的源极合并。

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