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11. 发明授权

US5928368A Method and apparatus for fault-tolerant multiprocessing system recovery from power failure or drop-outs 失效
标题翻译：用于容错多处理系统从断电或断电恢复的方法和装置
公开(公告)号：US5928368A
公开(公告)日：1999-07-27
申请号：US265585
申请日：1994-06-23
申请人： Robert L Jardine , Richard M. Collins , Larry D. Reeves
发明人： Robert L Jardine , Richard M. Collins , Larry D. Reeves
IPC分类号： G06F11/00
CPC分类号： G06F11/1441 , G06F11/1425
摘要： Multiple processors are connected to form a multiprocessor system having interprocessor communicating capability. In the face of a power-fail signal, indicating that possible power loss is imminent, a processor will proceed through a shut-down procedure to save the present operating state so that when power is re-applied the processor can continue from the operating state it left when power was lost. The shut-down procedure concludes with the processor broadcasting messages to all other processors that it is undergoing a power-fail shut-down which is noted by the other processors to later cause them to enter a cautious mode of operation so as to not exclude the processor in any system configuration involving agreement of all processors by reason of the processor's loss of power.
摘要翻译：连接多个处理器以形成具有处理器间通信能力的多处理器系统。在面临功率失效信号的情况下，指示可能的功率损耗即将来临，处理器将继续执行关闭程序以保存当前操作状态，使得当电源被重新施加时，处理器可以从操作状态继续当电力丢失时，它离开了。关闭程序结束于处理器向所有其他处理器广播消息，它正在进行电源故障关闭，由其他处理器注意到，以后使其进入谨慎的操作模式，以便不排除处理器在任何系统配置中涉及所有处理器的协议，因为处理器的功率损失。

12. 发明授权

US07388834B2 System and method for controlling network traffic flow in a multi-processor network 有权
标题翻译：用于控制多处理器网络中的网络流量的系统和方法
公开(公告)号：US07388834B2
公开(公告)日：2008-06-17
申请号：US09895577
申请日：2001-06-28
申请人： Sachin U. Naik , Robert L. Jardine , Tatsuhiro Torii
发明人： Sachin U. Naik , Robert L. Jardine , Tatsuhiro Torii
IPC分类号： H04L12/26
CPC分类号： H04L67/325 , H04L29/06 , H04L29/12018 , H04L47/10 , H04L47/28 , H04L61/10
摘要： A system and method for controlling network traffic flow in a multi-processor network is disclosed. The method employs a two-part algorithm to determine when it is appropriate for a client node to transmit data over a network to one or more server nodes. The first part of the algorithm calls for the client node to transmit data over the network after receiving an acknowledgement from one or more of the server nodes to which data transfer is outstanding. The second part of the algorithm provides for the client node transmitting data over the network after a predetermined time interval has elapsed since a data transmission. The time interval is based, in part, on the length of outstanding data packets and a statistical analysis of the number of nodes transmitting or receiving data packets. The transmission of data over the network is accomplished by a hybrid scheme, comprising a combination of PUSH and PULL transmission protocols.
摘要翻译：公开了一种用于控制多处理器网络中的网络业务流的系统和方法。该方法采用两部分算法来确定何时适合于客户端节点通过网络将数据传输到一个或多个服务器节点。该算法的第一部分要求客户端节点在从一个或多个数据传输未完成的服务器节点接收到确认之后，通过网络传输数据。该算法的第二部分提供了在从数据传输起经过预定时间间隔之后，客户机节点通过网络发送数据。时间间隔部分地基于未完成的数据分组的长度以及发送或接收数据分组的节点数量的统计分析。通过网络传输数据是通过混合方案实现的，包括PUSH和PULL传输协议的组合。

13. 发明授权

US5991518A Method and apparatus for split-brain avoidance in a multi-processor system 失效
标题翻译：在多处理器系统中分离脑避免的方法和装置
公开(公告)号：US5991518A
公开(公告)日：1999-11-23
申请号：US790269
申请日：1997-01-28
申请人： Robert L Jardine , Murali Basavaiah , Karoor S Krishnakumar
发明人： Robert L Jardine , Murali Basavaiah , Karoor S Krishnakumar
IPC分类号： G06F11/20 , G06F11/00 , G06F11/14 , G06F13/00
CPC分类号： G06F11/0724 , G06F11/1425 , G06F11/0757
摘要： A split brain avoidance protocol to determine the group of processors that will survive a complete partitioning (disconnection) in the inter-processor communications paths connecting processors in a multi-processor system. Processors embodying the invention detect that the set of processors with which they can communicate has changed. They then choose either to halt or to continue operations, guided by the goal of minimizing the possibility that multiple disconnected groups of processors continue to operate as independent systems, each group having determined (incorrectly) that the processors of the other groups have failed.
摘要翻译：一种分裂脑回避协议，用于确定能够在连接多处理器系统中的处理器的处理器间通信路径中的完全分区（断开）之后生存的处理器组。体现本发明的处理器检测出与其通信的处理器集合已经改变。然后他们选择停止或继续操作，其目标是尽量减少多个不连续的处理器组作为独立系统运行的可能性，每个组确定（错误地）其他组的处理器失败。

14. 发明授权

US5884018A Method and apparatus for distributed agreement on processor membership in a multi-processor system 失效
标题翻译：多处理器系统中处理器成员资格分配协议的方法和装置
公开(公告)号：US5884018A
公开(公告)日：1999-03-16
申请号：US789257
申请日：1997-01-28
申请人： Robert L. Jardine , Murali Basavaiah , Karoor S. Krishnakumar , Srinivasa D. Murthy
发明人： Robert L. Jardine , Murali Basavaiah , Karoor S. Krishnakumar , Srinivasa D. Murthy
IPC分类号： G06F11/20 , G06F11/00 , G06F11/14 , G06F13/00
CPC分类号： G06F11/0724 , G06F11/1425 , G06F11/0757
摘要： An apparatus and protocol to determine the group of processors that will survive communications faults and/or timed-event failures in a multiprocessor system. The processors each have a respective memory, and the processors are coupled by means of an inter-processor communication network. The processors detect that the set of processors with which they can communicate has changed. They can choose to either halt or continue operations based on minimizing the likelihood that disconnected groups of processors will continue to operate as independent systems. The processors construct a connectivity matrix on the initiation of a regroup operation. The connectivity information is used to ensure that all the processors in the final group that survives can communicate with all other processors in the group. One or more processors may halt to achieve this characteristic. A processor is suspected of having ceased operations or having a failed timer mechanism when other processors detect the absence of a periodic message from the processor. When this happens, all of the processors are subjected to a series of stages in which they repeatedly broadcast their status and connectivity to each other. The suspected processor does not advance through the stages if it has ceased operations or if its timer mechanism has failed.
摘要翻译：一种用于确定能够在多处理器系统中的通信故障和/或定时事件故障中存活的处理器组的装置和协议。处理器各自具有相应的存储器，并且处理器通过处理器间通信网络耦合。处理器检测到他们可以通信的一组处理器已经改变了。它们可以选择停止或继续操作，这是基于最小化不连续的处理器组作为独立系统继续运行的可能性。处理器在重组操作的启动时构建连接矩阵。连接信息用于确保最终组中存在的所有处理器可以与组中的所有其他处理器通信。一个或多个处理器可以停止以实现该特性。当其他处理器检测到处理器不存在周期性消息时，处理器被怀疑已经停止操作或发生故障定时器机制。当这种情况发生时，所有处理器都经历一系列的阶段，在这些阶段中，它们重复地将其状态和连接相互广播。怀疑的处理器如果停止运行或者其定时器机制失败，则不会进入阶段。

15. 发明申请

US20140131120A1 FOOT PAD DEVICE AND METHOD OF OBTAINING WEIGHT DATA 有权
标题翻译： FOOT PAD设备和获取重量数据的方法
公开(公告)号：US20140131120A1
公开(公告)日：2014-05-15
申请号：US14162553
申请日：2014-01-23
申请人： Robert W. HORST , Robert L. JARDINE , Jonathan SMITH , Edith ARNOLD
发明人： Robert W. HORST , Robert L. JARDINE , Jonathan SMITH , Edith ARNOLD
IPC分类号： A61B5/103 , G01G19/44
CPC分类号： A61B5/1036 , A61B5/1038 , G01G19/44 , G01G23/3735
摘要： A foot pad device includes a foot pad, force sensors that provide force data, sensor electronics coupled to the force sensors, and a processor. The foot pad includes a ball region configured to be located under a ball of the foot of the user or a heel region configured to be located under a heel of the foot of the user. At least a portion of the force sensors is located in the ball region or the heel region of the foot pad. The sensor electronics include a flexible circuit with force sensor connection paths adapted to transmit force data from the force sensors and are configured to condition the force data to be within a conditioned force data range. The processor is configured to calculate a weight value based on the conditioned force data, a gain value, and an offset value.
摘要翻译：足垫装置包括脚垫，提供力数据的力传感器，耦合到力传感器的传感器电子装置和处理器。足垫包括被配置为位于使用者的脚的球下方的球区域或被配置为位于使用者的脚的后跟下方的跟部区域。力传感器的至少一部分位于脚垫的球区域或跟部区域中。传感器电子器件包括柔性电路，其具有适于从力传感器传递力数据的力传感器连接路径，并且被配置为将力数据调节在调节的力数据范围内。处理器被配置为基于条件的力数据，增益值和偏移值来计算权重值。

16. 发明授权

US08230252B2 Time of day response 有权
标题翻译：时间响应
公开(公告)号：US08230252B2
公开(公告)日：2012-07-24
申请号：US10894784
申请日：2004-07-20
申请人： Robert L. Jardine , Russell M. Rector
发明人： Robert L. Jardine , Russell M. Rector
IPC分类号： G06F1/00
CPC分类号： G06F1/14
摘要： In an implementation of time of day response, time logic executed by each processor element of a logical processor generates a logical time in response to a time of day request. The logical time is generated to approximate the actual time such that each processor element of the logical processor returns the same logical time.
摘要翻译：在时间响应的实现中，由逻辑处理器的每个处理器元件执行的时间逻辑响应于时间请求而产生逻辑时间。生成逻辑时间以近似实际时间，使得逻辑处理器的每个处理器元件返回相同的逻辑时间。

17. 发明授权

US07434098B2 Method and system of determining whether a user program has made a system level call 失效
标题翻译：确定用户程序是否进行了系统级别调用的方法和系统
公开(公告)号：US07434098B2
公开(公告)日：2008-10-07
申请号：US11042981
申请日：2005-01-25
申请人： David L. Bernick , William F. Bruckert , David J. Garcia , Robert L. Jardine , Pankaj Mehra , James R. Smullen
发明人： David L. Bernick , William F. Bruckert , David J. Garcia , Robert L. Jardine , Pankaj Mehra , James R. Smullen
IPC分类号： G06F11/00
CPC分类号： G06F11/1658 , G06F9/52 , G06F11/1641 , G06F11/1645 , G06F11/165 , G06F11/1683 , G06F11/1687 , G06F11/184 , G06F11/185 , G06F11/3404 , G06F11/3476 , G06F11/3495 , G06F11/3636 , G06F11/366 , G06F2201/88
摘要： Method and system of determining whether a user program has made a system level call and thus whether the user program is uncooperative with fault tolerant operation. Some exemplary embodiments may be a processor-based method comprising providing information from a first processor to a second processor (the information indicating that a user program executed on the first processor has not made a system level call in a predetermined amount of time), and determining by the first processor, using information from the second processor, whether a duplicate copy of the user program substantially simultaneously executed in the second processor has made a system level call in the predetermined amount of time.
摘要翻译：确定用户程序是否进行了系统级别的调用以及用户程序是否不兼容容错操作的方法和系统。一些示例性实施例可以是基于处理器的方法，包括从第一处理器向第二处理器提供信息（指示在第一处理器上执行的用户程序在预定时间量内没有进行系统级别调用的信息），以及由第一处理器确定使用来自第二处理器的信息，在第二处理器中基本上同时执行的用户程序的副本是否在预定的时间量内进行了系统级的调用。

18. 发明授权

US07426656B2 Method and system executing user programs on non-deterministic processors 有权
标题翻译：在非确定性处理器上执行用户程序的方法和系统
公开(公告)号：US07426656B2
公开(公告)日：2008-09-16
申请号：US11042548
申请日：2005-01-25
申请人： David L. Bernick , William F. Bruckert , David J. Garcia , Robert L. Jardine , James S. Klecka , Pankaj Mehra , James R. Smullen
发明人： David L. Bernick , William F. Bruckert , David J. Garcia , Robert L. Jardine , James S. Klecka , Pankaj Mehra , James R. Smullen
IPC分类号： G06F11/00
CPC分类号： G06F11/1683 , G06F9/3851 , G06F9/3861 , G06F11/1482 , G06F11/1645 , G06F11/1691
摘要： A method and system of loosely lock-stepped non-deterministic processors. Some exemplary embodiments may be a processor-based method comprising executing fault tolerant copies of a user program, one copy of the user program executed in a first processor performing non-deterministic execution, and a duplicate copy of the user program executing in a second processor performing non-deterministic execution, with the executing in the first processor and second processor not in cycle-by-cycle lock-stepped.
摘要翻译：松散锁定非确定性处理器的方法和系统。一些示例性实施例可以是基于处理器的方法，包括执行用户程序的容错副本，在执行非确定性执行的第一处理器中执行的用户程序的一个副本以及在第二处理器中执行的用户程序的副本执行非确定性执行，其中在第一处理器和第二处理器中的执行不是按循环逐步锁定。

19. 发明授权

US06665811B1 Method and apparatus for checking communicative connectivity between processor units of a distributed system 失效
标题翻译：用于检查分布式系统的处理器单元之间的通信连接的方法和装置
公开(公告)号：US06665811B1
公开(公告)日：2003-12-16
申请号：US09645477
申请日：2000-08-24
申请人： Marcelo Moraes de Azevedo , Robert L. Jardine
发明人： Marcelo Moraes de Azevedo , Robert L. Jardine
IPC分类号： G06F1100
CPC分类号： G06F11/1425 , G06F11/202 , H04L43/50
摘要： An apparatus and protocol to determine the group of processors that will survive communications faults and/or timed-event failures in a distributed multiprocessor or clustered system. The processors are coupled to one another by an inter-processor communication network that is used, inter alia, by each processor to send path probe messages to each of the other processor units on all available network paths. A processor is suspected of being communicatively isolated, or having ceased operations, when one or more of the other processors detects the absence of an acknowledgment response from the processor. When this happens, all of the processors are subjected to a series of stages in which they repeatedly broadcast their status and connectivity to each other.
摘要翻译：一种用于确定能够在分布式多处理器或群集系统中的通信故障和/或定时事件故障中存活的处理器组的装置和协议。处理器通过处理器间通信网络相互耦合，处理器间通信网络尤其由每个处理器将路径探测消息发送到所有可用网络路径上的其他处理器单元中的每一个。当一个或多个其他处理器检测到来自处理器的确认响应不存在时，怀疑处理器被通信隔离或已经停止操作。当这种情况发生时，所有处理器都经历一系列的阶段，在这些阶段中，它们重复地将其状态和连接相互广播。

20. 发明授权

US5075844A Paired instruction processor precise exception handling mechanism 失效
标题翻译：配对指令处理器精度异常处理机制
公开(公告)号：US5075844A
公开(公告)日：1991-12-24
申请号：US357238
申请日：1989-05-24
申请人： Robert L. Jardine , Shannon J. Lynch , Philip R. Manela , Robert W. Horst
发明人： Robert L. Jardine , Shannon J. Lynch , Philip R. Manela , Robert W. Horst
IPC分类号： G06F9/38
CPC分类号： G06F9/3861
摘要： A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.

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