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1. 发明授权

US5075844A Paired instruction processor precise exception handling mechanism 失效
标题翻译：配对指令处理器精度异常处理机制
公开(公告)号：US5075844A
公开(公告)日：1991-12-24
申请号：US357238
申请日：1989-05-24
申请人： Robert L. Jardine , Shannon J. Lynch , Philip R. Manela , Robert W. Horst
发明人： Robert L. Jardine , Shannon J. Lynch , Philip R. Manela , Robert W. Horst
IPC分类号： G06F9/38
CPC分类号： G06F9/3861
摘要： A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.

2. 发明授权

US6009506A Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions 失效
公开(公告)号：US6009506A
公开(公告)日：1999-12-28
申请号：US59271
申请日：1998-04-10
申请人： Robert L. Jardine , Shannon J. Lynch , Philip R. Manela , Robert W. Horst
发明人： Robert L. Jardine , Shannon J. Lynch , Philip R. Manela , Robert W. Horst
IPC分类号： G06F9/26 , G06F9/38
CPC分类号： G06F9/3802 , G06F9/261 , G06F9/3838 , G06F9/3844 , G06F9/3853 , G06F9/3861
摘要： A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

3. 发明授权

US5072364A Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel 失效
标题翻译：在处理器中从不正确的分支预测中恢复的方法和装置，其执行并行指令的一系列
公开(公告)号：US5072364A
公开(公告)日：1991-12-10
申请号：US356316
申请日：1989-05-24
申请人： Robert L. Jardine , Shannon J. Lynch , Philip R. Manela , Robert W. Horst
发明人： Robert L. Jardine , Shannon J. Lynch , Philip R. Manela , Robert W. Horst
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/3844 , G06F9/3853
摘要： A branch recovery mechanism completes the processing of a concurrently issued family of instructions depending on the location of the branch instruction in the family and on whether the branch was correctly predicted. If the branch was not correctly predicted, the writes and stores of instructions in the family the precede the branch instruction are completed and those instructions are retired. However, the writes and stores of the instructions in the family following the branch instruction are inhibited.

4. 发明授权

US6035262A Real time observation serial scan test architecture 失效
标题翻译：实时观察串行扫描测试架构
公开(公告)号：US6035262A
公开(公告)日：2000-03-07
申请号：US266431
申请日：1994-06-27
申请人： Walter E. Gibson , Jeffery A. Sprouse , Eduardo M. Lipiansky , Javad Khakbaz , Michael A. Plum , Philip R. Manela , Ko Yamamoto
发明人： Walter E. Gibson , Jeffery A. Sprouse , Eduardo M. Lipiansky , Javad Khakbaz , Michael A. Plum , Philip R. Manela , Ko Yamamoto
IPC分类号： G01R31/3185 , H03K3/00
CPC分类号： G01R31/318555
摘要： Logic circuitry in the form of an integrated circuit includes a number of scannable registers located at various locations of the logic circuitry to continuously sample signal states thereat. In response to signalling from a maintenance diagnostic processor the scannable registers can be commanded to freeze their content for extraction and observation to determining the operating condition of the logic circuitry.
摘要翻译：集成电路形式的逻辑电路包括位于逻辑电路的不同位置的多个可扫描寄存器，用于连续地采样信号状态。响应于来自维护诊断处理器的信号，可以命令可扫描寄存器冻结其内容以进行提取和观察以确定逻辑电路的操作状态。

5. 发明授权

US07647467B1 Tuning DRAM I/O parameters on the fly 有权
标题翻译：即时调整DRAM I / O参数
公开(公告)号：US07647467B1
公开(公告)日：2010-01-12
申请号：US11642368
申请日：2006-12-19
申请人： Brian D. Hutsell , Sameer M. Gauria , Philip R. Manela , John A. Robinson
发明人： Brian D. Hutsell , Sameer M. Gauria , Philip R. Manela , John A. Robinson
IPC分类号： G06F12/00
CPC分类号： G06F13/4239
摘要： On the fly tuning of parameters used in an interface between a memory (e.g. high speed memory such as DRAM) and a processor requesting access to the memory. In an operational mode, a memory controller couples the processor to the memory. The memory controller can also inhibit the operational mode to initiate a training mode. In the training mode, the memory controller tunes one or more parameters (voltage references, timing skews, etc.) used in an upcoming operational mode. The access to the memory may be from an isochronous process running on a graphics processor. The memory controller determines whether the isochronous process may be inhibited before entering the training mode. If memory buffers for the isochronous process are such that the training mode will not impact the isochronous process, then the memory controller can enter the training mode to tune the interface parameters without negatively impacting the process.
摘要翻译：在用于存储器（例如，诸如DRAM的高速存储器）和请求访问存储器的处理器之间的接口中使用的参数的飞行调谐。在操作模式中，存储器控制器将处理器耦合到存储器。存储器控制器还可以禁止操作模式启动训练模式。在训练模式下，存储器控制器调节在即将到来的操作模式中使用的一个或多个参数（电压参考，时序偏移等）。对存储器的访问可以来自在图形处理器上运行的同步进程。存储器控制器确定在进入训练模式之前是否可以禁止同步过程。如果同步过程的存储器缓冲器使得训练模式不会影响同步过程，则存储器控制器可以进入训练模式以调整接口参数而不会不利地影响该过程。

6. 发明授权

US07015740B1 Self-adjusting programmable on-chip clock aligner 有权
标题翻译：自调整可编程片上时钟对准器
公开(公告)号：US07015740B1
公开(公告)日：2006-03-21
申请号：US10281503
申请日：2002-10-28
申请人： Eugene M. Feinberg , Richard F. Paul , Philip R. Manela
发明人： Eugene M. Feinberg , Richard F. Paul , Philip R. Manela
IPC分类号： H03H11/26
CPC分类号： G11C29/028 , G01R31/31725 , G06F1/04 , G11C29/02 , G11C29/50012 , H03L7/0805 , H03L7/0812 , H03L7/0997
摘要： A circuit including a sensing circuit, which includes a first delay circuit and a tuning circuit. The tuning circuit includes a sense counter and a reference counter. The sense counter is coupled to the first delay circuit and is configured to count a number of oscillations provided by the first delay circuit and provide a notification to the tuning circuit when the sense counter reaches a threshold value. The reference counter is coupled to the sense counter and a reference clock. The reference counter is configured to store a reference time which represents a time elapsed for the sense counter to reach the threshold value. Also included in the circuit is a second delay circuit coupled to the sensing circuit.
摘要翻译：一种包括感测电路的电路，其包括第一延迟电路和调谐电路。调谐电路包括感测计数器和参考计数器。感测计数器耦合到第一延迟电路，并且被配置为对由第一延迟电路提供的振荡数进行计数，并且当感测计数器达到阈值时向调谐电路提供通知。参考计数器耦合到感测计数器和参考时钟。参考计数器被配置为存储参考时间，其表示感测计数器经过的时间达到阈值。电路中还包括耦合到感测电路的第二延迟电路。

7. 发明授权

US5717695A Output pin for selectively outputting one of a plurality of signals internal to a semiconductor chip according to a programmable register for diagnostics 失效
标题翻译：输出引脚，用于根据用于诊断的可编程寄存器选择性地输出半导体芯片内部的多个信号中的一个
公开(公告)号：US5717695A
公开(公告)日：1998-02-10
申请号：US566900
申请日：1995-12-04
申请人： Philip R. Manela , Peter R. Birch , John C. Lin , Daniel R. Ullum
发明人： Philip R. Manela , Peter R. Birch , John C. Lin , Daniel R. Ullum
IPC分类号： G01R31/3183 , H03K19/173 , G11C29/00 , G01R31/28 , H03K19/003
CPC分类号： G01R31/318321 , H03K19/1732
摘要： A method of gaining access to multiple signals internal to a semiconductor chip while minimizing the number of pins dedicated for diagnostic and testing purposes. A chip designer determines which internal signals would most likely be helpful in troubleshooting and debugging a new chip design. These signals are input to a selector. A configuration register is loaded with information specifying which ones of these signals is to be routed to the output pin(s) so that they can be monitored externally by a logic analyzer in real-time. The selector only routes the currently designated signals to the appropriate output pin(s). Subsequently, a different set of signals can be selectively routed to the output pin(s) in place of the originally chosen signals.
摘要翻译：一种在半导体芯片内部访问多个信号的方法，同时最小化用于诊断和测试目的的引脚数量。芯片设计师确定哪些内部信号很有可能有助于排除和调试新的芯片设计。这些信号被输入到选择器。配置寄存器装载有指定这些信号中的哪些信号被路由到输出引脚的信息，使得它们可以由逻辑分析仪在外部被实时监测。选择器仅将当前指定的信号路由到适当的输出引脚。随后，可以将不同的信号集合选择性地路由到输出引脚，而不是原始选择的信号。

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