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1. 发明申请

US20100039052A1 ACTUATOR SYSTEM WITH A MULTI-MOTOR ASSEMBLY FOR EXTENDING AND FLEXING A JOINT 有权
标题翻译：具有多电机组件的执行器系统，用于扩展和弯曲接头
公开(公告)号：US20100039052A1
公开(公告)日：2010-02-18
申请号：US12191837
申请日：2008-08-14
申请人： Robert W. Horst , Kern Bhugra , Robert L. Jardine
发明人： Robert W. Horst , Kern Bhugra , Robert L. Jardine
IPC分类号： H02P5/69
CPC分类号： A61H1/0237 , A61H1/024 , A61H1/0266 , A61H1/0274 , A61H1/0277 , A61H1/0281 , A61H2201/1215 , A61H2201/1445 , A61H2201/1463 , A61H2201/149 , A61H2201/5061 , A61H2201/5064 , F16H25/20 , F16H2025/2081
摘要： An actuator system for extending and flexing a joint, including a multi-motor assembly for providing a rotational output, a rotary-to-linear mechanism for converting the rotational output from the multi-motor assembly into an extension and flexion of the joint, and a controller for operating the actuator system in several operational modes. The multi-motor assembly preferably combines power from two different sources, such that the multi-motor assembly can supply larger forces at slower speeds (“Low Gear”) and smaller forces at higher speeds (“High Gear”). The actuator has been specifically designed for extending and flexing a joint (such as an ankle, a knee, an elbow, or a shoulder) of a human. The actuator system may, however, be used to move any suitable object through any suitable movement (linear, rotational, or otherwise).
摘要翻译：一种用于延伸和弯曲接头的致动器系统，包括用于提供旋转输出的多电机组件，用于将来自多电动机组件的旋转输出转换成接头的伸展和弯曲的旋转到线性机构，以及用于以多种操作模式操作致动器系统的控制器。多电动机组件优选地组合来自两个不同源的动力，使得多电动机组件可以以较低速度（“低齿轮”）和较高速度（“高齿轮”）下的较小力提供较大的力。致动器专门设计用于伸展和弯曲人体的关节（例如脚踝，膝盖，肘部或肩部）。然而，致动器系统可以用于通过任何合适的运动（线性，旋转或其他方式）移动任何合适的物体。

2. 发明申请

US20090306548A1 THERAPEUTIC METHOD AND DEVICE FOR REHABILITATION 审中-公开
标题翻译：治疗方法和康复装置
公开(公告)号：US20090306548A1
公开(公告)日：2009-12-10
申请号：US12134095
申请日：2008-06-05
申请人： Kern S. BHUGRA , Robert W. Horst , Robert L. Jardine
发明人： Kern S. BHUGRA , Robert W. Horst , Robert L. Jardine
IPC分类号： A61B5/103 , A61B19/00 , A61H1/02
CPC分类号： A61H1/008 , A61H1/024 , A61H1/0266 , A61H2201/165 , A61H2201/5015 , A61H2201/5038 , A61H2201/5061 , A61H2201/5064 , A61H2201/5069 , A61H2230/65 , A63B21/00181 , A63B21/0054
摘要： The invention relates to embodiments of methods for extending a subject-controllable range of joint motion, and for increasing subject control of joint movement within a range of motion. Embodiments include fastening a powered device around a joint so as to be able to control the joint, allowing the subject to move the joint within a range of volitional motion, and then engaging the powered device to support movement of the joint into an expanded, rehabilitative range. In some embodiments, the device supports joint movement by substantially providing the force to move the joint beyond the volitional boundary. In other embodiments, supporting movement includes the subject substantially providing the force, and the device allowing movement only in a desired direction. The invention further relates to a system for increasing the functional capability of a joint by implementing embodiments of the method. By such methods and system, rehabilitation is accomplished both by building strength, and training neural pathways.
摘要翻译：本发明涉及用于扩展受试者可控制的关节运动范围的方法的实施例，并且用于在运动范围内增加关节运动的受试者控制。实施例包括将动力装置紧固在关节周围以便能够控制关节，允许受试者在一定范围内移动关节，然后与动力装置接合以支持关节的运动进入扩张的康复范围。在一些实施例中，装置通过基本上提供使联接件移动超过界限的力来支撑关节运动。在其他实施例中，支撑运动包括受试者基本上提供力，并且该装置允许仅在所需方向上移动。本发明还涉及通过实施该方法来增加关节的功能能力的系统。通过这种方法和系统，通过建立实力和训练神经通路来实现康复。

3. 发明授权

US07308605B2 Latent error detection 有权
标题翻译：潜在错误检测
公开(公告)号：US07308605B2
公开(公告)日：2007-12-11
申请号：US10894825
申请日：2004-07-20
申请人： Robert L. Jardine , David L. Bernick , Thomas A. Heynemann , James R. Smullen
发明人： Robert L. Jardine , David L. Bernick , Thomas A. Heynemann , James R. Smullen
IPC分类号： G06F11/00
CPC分类号： G06F11/1666 , G06F11/1004 , G06F11/1633
摘要： In an implementation of latent error detection, memory regions that each correspond to a different processor element of a redundant processor system are scanned for latent processing errors maintained as erroneous data. The data maintained in the memory regions is compared to detect a latent processing error in a first memory region. The latent processing error is resolved by copying data from a second memory region into the first memory region where the data maintained in the second memory region is determined to be identical to data maintained in at least a third memory region.
摘要翻译：在潜在错误检测的实现中，扫描每个对应于冗余处理器系统的不同处理器元件的存储器区域作为错误数据维护的潜在处理错误。将保存在存储器区域中的数据进行比较，以检测第一存储器区域中的潜在处理误差。通过将数据从第二存储器区域复制到第一存储器区域中来解决潜在处理错误，其中保持在第二存储器区域中的数据被确定为与至少第三存储器区域中保持的数据相同。

4. 发明授权

US06195754B1 Method and apparatus for tolerating power outages of variable duration in a multi-processor system 失效
标题翻译：用于在多处理器系统中容忍可变持续时间的停电的方法和装置
公开(公告)号：US06195754B1
公开(公告)日：2001-02-27
申请号：US08789260
申请日：1997-01-28
申请人： Robert L. Jardine , Larry D. Reeves , Murali Basavaiah , Garry Easop
发明人： Robert L. Jardine , Larry D. Reeves , Murali Basavaiah , Garry Easop
IPC分类号： G06F130
CPC分类号： G06F1/30
摘要： An apparatus and method for tolerating failure of the AC power source in a power supply switchable between the AC power source and a battery, in a processor system having a set of one or more components subject to being powered down. When the failure of the AC power source is recognized, the power supply is switched from the AC power source to the battery. For a first period of time, the battery powers the processor system with all components powered on. The battery then powers the processor system with the specific set of components powered off for a second period of time. In one embodiment, a determination is made that the battery can power the processor system with the set of components powered down for a predetermined period of time. A determination of the first period of time is then made as the capacity of the battery exceeding the predetermined period of time, if the excess capacity is used to power the processor system with the set of components powered on. In effect, a processor system incorporating one embodiment of the invention rides through a first period of a power outage, operating as normal and masking the loss of AC power. For a second, predetermined period, the processor system shuts down optional hardware and maintains the state of memory using the battery power.
摘要翻译：一种用于在具有一组一个或多个要断电的组件的处理器系统中容忍在可切换于AC电源和电池之间的电源中的交流电源故障的装置和方法。当识别到交流电源的故障时，电源从交流电源切换到电池。在第一段时间内，电池为处理器系统供电，所有组件都通电。然后电池为处理器系统供电，特定组件在第二个时间段内关闭。在一个实施例中，确定电池可以以一组组件断电一段预定时间来为处理器系统供电。然后，如果使用多余的容量来为处理器系统供电，则该电池的容量将超过预定时间段，则第一时间段的确定被做成。实际上，结合本发明一个实施例的处理器系统沿着停电的第一周期操作，正常工作并掩盖AC电力的损失。在第二个预定时间段内，处理器系统关闭可选硬件并使用电池电源维持存储器的状态。

5. 发明授权

US5687308A Method to improve tolerance of non-homogeneous power outages 失效
标题翻译：提高非均匀停电容忍度的方法
公开(公告)号：US5687308A
公开(公告)日：1997-11-11
申请号：US487941
申请日：1995-06-07
申请人： Robert L. Jardine , Richard M. Collins , A. Richard Zacher
发明人： Robert L. Jardine , Richard M. Collins , A. Richard Zacher
IPC分类号： G06F11/14 , G06F11/00
CPC分类号： G06F11/1425 , G06F11/142
摘要： Multiple processors are connected to form a multiprocessor system having inter-processor communicating capability. Each processor maintains a configuration option register indicating the resources necessary to operate the multiprocessor system. In the event of a power-fail signal, indicating that possible power loss is imminent, a processor will proceed through a shut-down procedure to save the present operating state so that when power is re-applied the processor can continue from the operating state it left when power was lost. Those processors not receiving a power-fail signal will attempt to reconfigure the multiprocessor system, waiting a reasonable amount of time for the processor receiving the power-fail signal to continue operations. If the processor has not recovered from the power-fail signal after a reasonable amount of time, the other processors check the configuration option register to determine whether that processor is necessary for operation of the multiprocessor system. If it is, then the processors wait for the processor according to a formula specified in said reconfiguration option register. Otherwise, the processors exclude the processor from the system and continue operation without the excluded processors.
摘要翻译：连接多个处理器以形成具有处理器间通信能力的多处理器系统。每个处理器维护配置选项寄存器，指示操作多处理器系统所需的资源。在发生电源故障信号的情况下，指示可能的功率损耗即将来临，处理器将继续执行关闭程序以保存当前的工作状态，使得当电源被重新施加时，处理器可以从操作状态继续当电力丢失时，它离开了。未接收到电源故障信号的那些处理器将尝试重新配置多处理器系统，等待处理器接收到电源故障信号的合理时间来继续运行。如果处理器在合理的时间内没有从电源故障信号中恢复，则其他处理器检查配置选项寄存器以确定该处理器是否需要用于多处理器系统的操作。如果是，则处理器根据所述重新配置选项寄存器中指定的公式等待处理器。否则，处理器将处理器从系统中排除，并在没有排除的处理器的情况下继续操作。

6. 发明授权

US08058823B2 Actuator system with a multi-motor assembly for extending and flexing a joint 有权
标题翻译：具有多马达组件的执行器系统，用于延伸和弯曲接头
公开(公告)号：US08058823B2
公开(公告)日：2011-11-15
申请号：US12191837
申请日：2008-08-14
申请人： Robert W. Horst , Kern Bhugra , Robert L. Jardine
发明人： Robert W. Horst , Kern Bhugra , Robert L. Jardine
IPC分类号： H02P5/00
CPC分类号： A61H1/0237 , A61H1/024 , A61H1/0266 , A61H1/0274 , A61H1/0277 , A61H1/0281 , A61H2201/1215 , A61H2201/1445 , A61H2201/1463 , A61H2201/149 , A61H2201/5061 , A61H2201/5064 , F16H25/20 , F16H2025/2081
摘要： An actuator system for extending and flexing a joint, including a multi-motor assembly for providing a rotational output, a rotary-to-linear mechanism for converting the rotational output from the multi-motor assembly into an extension and flexion of the joint, and a controller for operating the actuator system in several operational modes. The multi-motor assembly preferably combines power from two different sources, such that the multi-motor assembly can supply larger forces at slower speeds (“Low Gear”) and smaller forces at higher speeds (“High Gear”). The actuator has been specifically designed for extending and flexing a joint (such as an ankle, a knee, an elbow, or a shoulder) of a human. The actuator system may, however, be used to move any suitable object through any suitable movement (linear, rotational, or otherwise).
摘要翻译：一种用于延伸和弯曲接头的致动器系统，包括用于提供旋转输出的多电机组件，用于将来自多电动机组件的旋转输出转换成接头的伸展和弯曲的旋转到线性机构，以及用于以多种操作模式操作致动器系统的控制器。多电动机组件优选地组合来自两个不同源的动力，使得多电动机组件可以以较低速度（“低齿轮”）和较高速度（“高齿轮”）下的较小力提供较大的力。致动器专门设计用于伸展和弯曲人体的关节（例如脚踝，膝盖，肘部或肩部）。然而，致动器系统可以用于通过任何合适的运动（线性，旋转或其他方式）移动任何合适的物体。

7. 发明授权

US07933966B2 Method and system of copying a memory area between processor elements for lock-step execution 有权
标题翻译：在处理器元件之间复制存储区域以进行锁步执行的方法和系统
公开(公告)号：US07933966B2
公开(公告)日：2011-04-26
申请号：US11114318
申请日：2005-04-26
申请人： Thomas J. Kondo , Robert L. Jardine , James S. Klecka , William F. Bruckert , David J. Garcia , James R. Smullen , Patrick H. Barnes
发明人： Thomas J. Kondo , Robert L. Jardine , James S. Klecka , William F. Bruckert , David J. Garcia , James R. Smullen , Patrick H. Barnes
IPC分类号： G06F15/167
CPC分类号： G06F11/1658 , G06F9/3824 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F11/1683 , G06F11/1687 , G06F11/185
摘要： A method and system of copying a memory area between processor elements for lock-step execution. At least some of the illustrative embodiments may be a method comprising executing duplicate copies of a first program in a first processor of a first multiprocessor computer system and in a first processor of a second multiprocessor computer system (the executing substantially in lock-step), executing a second program in a second processor element of the first multiprocessor computer system (the first and second processors of the first multiprocessor computer system sharing an input/output (I/O) bridge), copying a memory area of the second program executing in the second processor element of the first multiprocessor computer system to a memory of a second processor element in the second multiprocessor computer system while the duplicate copies of the first program are executing in the first processor elements, and then executing duplicate copies of the second program in the second processors in lock-step.
摘要翻译：在处理器元件之间复制存储区域以进行锁步执行的方法和系统。示例性实施例中的至少一些可以是包括在第一多处理器计算机系统的第一处理器和第二多处理器计算机系统的第一处理器中执行第一程序的重复副本（执行基本上是锁定步骤）的方法，在第一多处理器计算机系统的第二处理器元件（共享输入/输出（I / O）桥的第一多处理器计算机系统的第一和第二处理器）中执行第二程序，复制第二程序中执行的第二程序的存储区域所述第一多处理器计算机系统的第二处理器元件到所述第二多处理器计算机系统中的第二处理器元件的存储器，同时所述第一程序的副本在所述第一处理器元件中执行，然后执行所述第二程序的副本第二个处理器在锁步。

8. 发明授权

US07764689B2 Method and apparatus for arbitrating data packets in a network system 有权
标题翻译：用于在网络系统中仲裁数据分组的方法和装置
公开(公告)号：US07764689B2
公开(公告)日：2010-07-27
申请号：US11229109
申请日：2005-09-16
申请人： David L. Bernick , Robert L. Jardine , Marcelo M. de Azevedo
发明人： David L. Bernick , Robert L. Jardine , Marcelo M. de Azevedo
IPC分类号： H04L12/28
CPC分类号： H04L45/34 , H04L45/02 , H04L45/24 , H04L45/72 , H04L47/50 , H04L47/56 , H04L47/562 , H04L47/568 , H04L47/623 , H04L47/6255
摘要： Techniques for routing data packets in a networked system. Specifically, a network system and methods of arbitrating data packets in a network system are provided. Switching devices are configured to receive one or more data packets, wherein each of the one or more data packets includes a respective source identification. The source identifications are compared to a source identification history mechanism, and the routing order of the data packets is determined based on the comparison.
摘要翻译：在网络系统中路由数据包的技术。具体地说，提供网络系统和网络系统中的数据分组仲裁方法。交换设备被配置为接收一个或多个数据分组，其中所述一个或多个数据分组中的每一个包括相应的源标识。将源标识与源识别历史机制进行比较，并且基于比较确定数据分组的路由顺序。

9. 发明申请

US20090070564A1 METHOD AND SYSTEM OF ALIGNING EXECUTION POINT OF DUPLICATE COPIES OF A USER PROGRAM BY EXCHANGING INFORMATION ABOUT INSTRUCTIONS EXECUTED 失效
标题翻译：通过交换指令执行的用户程序的复制执行点的方法和系统
公开(公告)号：US20090070564A1
公开(公告)日：2009-03-12
申请号：US12269945
申请日：2008-11-13
申请人： Paul Del Vigna, JR. , Robert L. Jardine
发明人： Paul Del Vigna, JR. , Robert L. Jardine
IPC分类号： G06F9/30
CPC分类号： G06F9/3851
摘要： Aligning execution point of duplicate copies of a user program by exchanging information about instructions executed. At least some of the exemplary embodiments may be a method of operating duplicate copies of a user program in a first and second processor, allowing at least one of the user programs to execute until retired instruction counter values in each processor are substantially the same, and then executing a number of instructions of each user program. Of the instructions executed, at least some of the instructions are decoded and the inputs of each decoded instruction determined (the decoding substantially simultaneously with executing in each processor). The method further may include exchanging among the processors addresses of decoded instructions and values indicative of inputs of the decoded instructions, determining that an execution point of the user program in the first processor lags with respect to an execution point of the user program in the second processor using at least the addresses of the decoded instructions, and advancing the first processor until the execution point within each user program is substantially aligned.
摘要翻译：通过交换有关执行指令的信息来对齐用户程序的副本的执行点。示例性实施例中的至少一些可以是在第一和第二处理器中操作用户程序的重复副本的方法，允许至少一个用户程序执行，直到每个处理器中的退休指令计数器值基本相同，以及然后执行每个用户程序的多个指令。在执行的指令中，至少一些指令被解码，并且每个解码指令的输入被确定（基本上同时在每个处理器中执行的解码）。该方法还可以包括在处理器之间交换解码指令的地址和指示解码指令的输入的值，确定第一处理器中的用户程序的执行点相对于第二处理器中的用户程序的执行点滞后使用至少解码指令的地址，以及推进第一处理器，直到每个用户程序内的执行点基本对准。

10. 发明授权

US6009506A Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions 失效
公开(公告)号：US6009506A
公开(公告)日：1999-12-28
申请号：US59271
申请日：1998-04-10
申请人： Robert L. Jardine , Shannon J. Lynch , Philip R. Manela , Robert W. Horst
发明人： Robert L. Jardine , Shannon J. Lynch , Philip R. Manela , Robert W. Horst
IPC分类号： G06F9/26 , G06F9/38
CPC分类号： G06F9/3802 , G06F9/261 , G06F9/3838 , G06F9/3844 , G06F9/3853 , G06F9/3861
摘要： A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

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