会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Method and apparatus for distributed agreement on processor membership
in a multi-processor system
    • 多处理器系统中处理器成员资格分配协议的方法和装置
    • US5884018A
    • 1999-03-16
    • US789257
    • 1997-01-28
    • Robert L. JardineMurali BasavaiahKaroor S. KrishnakumarSrinivasa D. Murthy
    • Robert L. JardineMurali BasavaiahKaroor S. KrishnakumarSrinivasa D. Murthy
    • G06F11/20G06F11/00G06F11/14G06F13/00
    • G06F11/0724G06F11/1425G06F11/0757
    • An apparatus and protocol to determine the group of processors that will survive communications faults and/or timed-event failures in a multiprocessor system. The processors each have a respective memory, and the processors are coupled by means of an inter-processor communication network. The processors detect that the set of processors with which they can communicate has changed. They can choose to either halt or continue operations based on minimizing the likelihood that disconnected groups of processors will continue to operate as independent systems. The processors construct a connectivity matrix on the initiation of a regroup operation. The connectivity information is used to ensure that all the processors in the final group that survives can communicate with all other processors in the group. One or more processors may halt to achieve this characteristic. A processor is suspected of having ceased operations or having a failed timer mechanism when other processors detect the absence of a periodic message from the processor. When this happens, all of the processors are subjected to a series of stages in which they repeatedly broadcast their status and connectivity to each other. The suspected processor does not advance through the stages if it has ceased operations or if its timer mechanism has failed.
    • 一种用于确定能够在多处理器系统中的通信故障和/或定时事件故障中存活的处理器组的装置和协议。 处理器各自具有相应的存储器,并且处理器通过处理器间通信网络耦合。 处理器检测到他们可以通信的一组处理器已经改变了。 它们可以选择停止或继续操作,这是基于最小化不连续的处理器组作为独立系统继续运行的可能性。 处理器在重组操作的启动时构建连接矩阵。 连接信息用于确保最终组中存在的所有处理器可以与组中的所有其他处理器通信。 一个或多个处理器可以停止以实现该特性。 当其他处理器检测到处理器不存在周期性消息时,处理器被怀疑已经停止操作或发生故障定时器机制。 当这种情况发生时,所有处理器都经历一系列的阶段,在这些阶段中,它们重复地将其状态和连接相互广播。 怀疑的处理器如果停止运行或者其定时器机制失败,则不会进入阶段。
    • 4. 发明授权
    • Direct bulk data transfers
    • 直接批量数据传输
    • US5805920A
    • 1998-09-08
    • US556618
    • 1995-11-13
    • Todd W. SprenkleSrinivasa D. MurthyAnil Khatri
    • Todd W. SprenkleSrinivasa D. MurthyAnil Khatri
    • G06F15/16G06F9/46G06F11/20G06F15/177G06F13/00
    • G06F9/544G06F11/2035G06F11/2046G06F11/2071G06F11/2089
    • A data processing system for transferring data is provided. This system includes central processing units (CPUs 20, 22, 24 and 26) and storage units (30 and 32 with 100-105 and 110-115) which are interconnected by a network (10). The CPUs (20, 22, 24 and 26) include a request process (133) and a storage process (130). The storage process (130) controls access to the storage unit (30 with 100-105 and 110-115). Software routines (220) are used to provide direct access to the storage unit (30 with 100-105 and 110-115) by the request CPU (22). The request CPU (20) is the CPU containing the request process (133). A virtual memory address for a buffer (160) of the request CPU (22) is created in the request CPU (22). The virtual memory address along with a storage unit access request are sent to the CPU (20) containing the storage process (130). A work request including the virtual memory address to sent from the storage process (130) to the storage unit (30 with 100-105 and 110-115). The data is then transferred directly between the request CPU (22) and the storage unit (30 with 100-105 and 110-115). The storage unit (30 with 100-105 and 110-115) then responds to the work request.
    • 提供了一种用于传送数据的数据处理系统。 该系统包括由网络(10)互连的中央处理单元(CPU 20,22,24和26)以及具有100-105和110-115的存储单元(30和32)。 CPU(20,22,24和26)包括请求处理(133)和存储处理(130)。 存储处理(130)控制对具有100-105和110-115的存储单元(30)的访问。 软件程序(220)用于通过请求CPU(22)直接访问具有100-105和110-115的存储单元(30)。 请求CPU(20)是包含请求处理(133)的CPU。 在请求CPU(22)中创建请求CPU(22)的缓冲器(160)的虚拟存储器地址。 虚拟存储器地址以及存储单元访问请求被发送到包含存储处理(130)的CPU(20)。 一种工作请求,其包括从存储处理(130)发送到存储单元(30-10,具有100-105和110-115)的虚拟存储器地址。 然后,数据直接在请求CPU(22)和存储单元(30〜100〜105和110-115)之间传送。 存储单元(30与100-105和110-115)然后响应工作请求。
    • 7. 发明授权
    • Method an apparatus for tolerance of lost timer ticks during recovery of
a multi-processor system
    • 方法在恢复多处理器系统期间容忍丢失定时器滴答的装置
    • US5892895A
    • 1999-04-06
    • US790268
    • 1997-01-28
    • Murali BasavaiahKaroor S. KrishnakumaSrinivasa D. Murthy
    • Murali BasavaiahKaroor S. KrishnakumaSrinivasa D. Murthy
    • G06F11/20G06F11/00G06F11/14
    • H04L69/28G06F11/1425H04L69/40
    • A method and apparatus for detecting and tolerating situations in which one or more processors in a multi-processor system cannot participate in timer-driven or timer-triggered protocols or event sequences. The multi-processor system includes multiple processors each having a respective memory. These processors are coupled by an inter-processor communication network (preferably consisting of redundant paths).Processors are suspected of having failed (ceased operations) outright or having a failed timer mechanism when other processors detect the absence of periodic "IamAlive" messages from other processors. When this happens, all of the processors in the system are subjected to a series of stages in which they repeatedly broadcast their status and their connectivity to each other. During the first such stage, according to the present invention, a processor will not assert its ability to participate unless its timer mechanism is working. It arms a timer expiration event and does not assert its health until and unless that timer expiration event occurs.
    • 一种用于检测和容忍多处理器系统中的一个或多个处理器不能参与定时器驱动或定时器触发的协议或事件序列的情况的方法和装置。 多处理器系统包括多个具有相应存储器的处理器。 这些处理器通过处理器间通信网络(优选地由冗余路径组成)耦合。 当其他处理器检测到不存在来自其他处理器的周期性“IamAlive”消息时,处理器被怀疑已经失败(停止操作)或定时器机制失败。 当这种情况发生时,系统中的所有处理器都经历一系列阶段,在这些阶段中,它们重复地广播其状态及其彼此的连接。 在第一个这样的阶段期间,根据本发明,处理器将不会断言其参与的能力,除非其定时器机制正在工作。 它会阻止定时器到期事件,并且除非发生定时器到期事件,否则不会断言其状态。