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1. 发明授权

US08799706B2 Method and system of exchanging information between processors 有权
标题翻译：处理器之间交换信息的方法和系统
公开(公告)号：US08799706B2
公开(公告)日：2014-08-05
申请号：US11042985
申请日：2005-01-25
申请人： William F. Bruckert , David J. Garcia , Thomas A. Heynemann , James S. Klecka , Jeffrey A. Sprouse
发明人： William F. Bruckert , David J. Garcia , Thomas A. Heynemann , James S. Klecka , Jeffrey A. Sprouse
IPC分类号： G06F11/00
CPC分类号： G06F11/1687 , G06F11/1645
摘要： A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a user program by the first processor, writing (by a second processor) a second datum to the logic device and then continuing processing of a user program by the second processor, and writing (by the logic device) the first and second datum to each of the first and second processors after all the processors have written their respective datum to the logic device.
摘要翻译：一种在处理器之间交换信息的方法和系统。说明性实施例中的至少一些可以是一种方法，包括通过将（第一处理器）第一数据写入逻辑设备，然后由第一处理器继续处理用户程序，在多个处理器之间交换信息，由（第第二处理器）到逻辑设备的第二数据，然后由第二处理器继续处理用户程序，并且在所有处理器具有第一处理器和第二处理器之后，通过逻辑器件将第一和第二数据写入第一和第二处理器将其各自的基准写入逻辑设备。

2. 发明授权

US07516358B2 Tuning core voltages of processors 有权
标题翻译：调整处理器的核心电压
公开(公告)号：US07516358B2
公开(公告)日：2009-04-07
申请号：US11312201
申请日：2005-12-20
申请人： Juerg Haefliger , William F. Bruckert , James S. Klecka
发明人： Juerg Haefliger , William F. Bruckert , James S. Klecka
IPC分类号： G06F11/00
CPC分类号： G06F11/24
摘要： A method, apparatus, and system are disclosed for tuning core voltages of processors. One embodiment is a method for software execution. The method includes varying core voltages of plural processors operating in lockstep to determine an operating range for each of the plural processors, and adjusting the core voltages of the plural processors within the operating range to tune the plural processors.
摘要翻译：公开了一种用于调整处理器的核心电压的方法，装置和系统。一个实施例是用于软件执行的方法。该方法包括改变在锁步骤中操作的多个处理器的核心电压，以确定多个处理器中的每一个的操作范围，以及调整该操作范围内的多个处理器的核心电压以调谐多个处理器。

3. 发明授权

US06604177B1 Communication of dissimilar data between lock-stepped processors 失效
标题翻译：在锁阶处理器之间传送不同的数据
公开(公告)号：US06604177B1
公开(公告)日：2003-08-05
申请号：US09676403
申请日：2000-09-29
申请人： Thomas J. Kondo , James S. Klecka
发明人： Thomas J. Kondo , James S. Klecka
IPC分类号： G06F1200
CPC分类号： G06F11/1695 , G06F11/1641 , G06F11/165 , G06F11/1654 , G06F11/1658
摘要： A processing system includes a pair of processor coupled in a lockstep arrangement. The pair of processors is coupled to a storage element that is external to the both of them. Each processor executes an instruction stream that is identical to that executed by the other. Dissimilar information can be exchanged between the processors by each writing the information they wish to exchange to a first storage location with identical instructions. Although both processors execute the write with the same address, the information written by one of the processors is redirected to a second storage location. Each processor then reads the first and second storage locations to retrieve information supplied by the other processor. Now each processor has a copy of the other's data while staying in lockstep.
摘要翻译：一种处理系统包括以锁定装置耦合的一对处理器。一对处理器耦合到两者之外的存储元件。每个处理器执行与另一个执行的指令流相同的指令流。可以在处理器之间通过每个将他们希望交换的信息写入具有相同指令的第一存储位置来交换不同信息。虽然两个处理器执行具有相同地址的写入，但是由一个处理器写入的信息被重定向到第二存储位置。然后，每个处理器读取第一和第二存储位置以检索由另一个处理器提供的信息。现在每个处理器都保留对方数据的副本。

4. 发明授权

US06360284B1 System for protecting output drivers connected to a powered-off load 有权
标题翻译：用于保护连接到掉电负载的输出驱动器的系统
公开(公告)号：US06360284B1
公开(公告)日：2002-03-19
申请号：US09231407
申请日：1999-01-13
申请人： John M. Brown , William P. Bunton , James S. Klecka , Charles E. Peet, Jr. , David A. Brown
发明人： John M. Brown , William P. Bunton , James S. Klecka , Charles E. Peet, Jr. , David A. Brown
IPC分类号： G06F1314
CPC分类号： G06F13/4072
摘要： A system for preventing a powered-up sub-unit from driving a powered-off low-impedance load transitions to a NO_CLOCK state and tri-states output drivers of the sub-unit output unless a clock signal is received from a connected sub-unit. While in the NO_CLOCK state, the sub-unit periodically transmits bursts of clock signals to signal the other sub-unit that it is powered up.
摘要翻译：用于防止加电子单元驱动掉电的低阻抗负载的系统转换到NO_CLOCK状态，并且三态地指示子单元输出的输出驱动器，除非从连接的子单元接收到时钟信号。当处于NO_CLOCK状态时，子单元周期性地发送脉冲串的时钟信号，以向被加电的另一个子单元发出信号。

5. 发明授权

US07549082B2 Method and system of bringing processors to the same computational point 失效
标题翻译：将处理器带到同一个计算点的方法和系统
公开(公告)号：US07549082B2
公开(公告)日：2009-06-16
申请号：US11350315
申请日：2006-02-03
申请人： Dale E. Southgate , Mihai Damian , Peter A. Reynolds , William F. Bruckert , James S. Klecka
发明人： Dale E. Southgate , Mihai Damian , Peter A. Reynolds , William F. Bruckert , James S. Klecka
IPC分类号： G06F11/00
CPC分类号： G05B19/0428 , G05B2219/24187
摘要： A method and system of bringing processors to the same computational point. At least some of the illustrative embodiments are computer systems comprising a first processor executing a program, a second processor executing a duplicate copy of the program (but at different computational points in the program), and a shared main memory coupled to the first and second processors. When the processors each receive duplicate copies of an interrupt request, the processors are configured to bring their respective programs to the same computational points prior to servicing the interrupt request.
摘要翻译：将处理器带到同一个计算点的方法和系统。至少一些说明性实施例是包括执行程序的第一处理器，执行程序的重复副本（但在程序中的不同计算点处）的第二处理器的计算机系统以及耦合到第一和第二处理器。当处理器每个接收到中断请求的重复副本时，处理器被配置为在服务中断请求之前将它们各自的程序带到相同的计算点。

6. 发明授权

US07426656B2 Method and system executing user programs on non-deterministic processors 有权
标题翻译：在非确定性处理器上执行用户程序的方法和系统
公开(公告)号：US07426656B2
公开(公告)日：2008-09-16
申请号：US11042548
申请日：2005-01-25
申请人： David L. Bernick , William F. Bruckert , David J. Garcia , Robert L. Jardine , James S. Klecka , Pankaj Mehra , James R. Smullen
发明人： David L. Bernick , William F. Bruckert , David J. Garcia , Robert L. Jardine , James S. Klecka , Pankaj Mehra , James R. Smullen
IPC分类号： G06F11/00
CPC分类号： G06F11/1683 , G06F9/3851 , G06F9/3861 , G06F11/1482 , G06F11/1645 , G06F11/1691
摘要： A method and system of loosely lock-stepped non-deterministic processors. Some exemplary embodiments may be a processor-based method comprising executing fault tolerant copies of a user program, one copy of the user program executed in a first processor performing non-deterministic execution, and a duplicate copy of the user program executing in a second processor performing non-deterministic execution, with the executing in the first processor and second processor not in cycle-by-cycle lock-stepped.
摘要翻译：松散锁定非确定性处理器的方法和系统。一些示例性实施例可以是基于处理器的方法，包括执行用户程序的容错副本，在执行非确定性执行的第一处理器中执行的用户程序的一个副本以及在第二处理器中执行的用户程序的副本执行非确定性执行，其中在第一处理器和第二处理器中的执行不是按循环逐步锁定。

7. 发明授权

US07590885B2 Method and system of copying memory from a source processor to a target processor by duplicating memory writes 有权
标题翻译：通过复制存储器写入将存储器从源处理器复制到目标处理器的方法和系统
公开(公告)号：US07590885B2
公开(公告)日：2009-09-15
申请号：US11114319
申请日：2005-04-26
申请人： Thomas J. Kondo , Robert L Jardine , William F. Bruckert , David J. Garcia , James S. Klecka , James R. Smullen , Jeff Sprouse , Graham B. Stott
发明人： Thomas J. Kondo , Robert L Jardine , William F. Bruckert , David J. Garcia , James S. Klecka , James R. Smullen , Jeff Sprouse , Graham B. Stott
IPC分类号： G06F11/00
CPC分类号： G06F11/1658
摘要： A method and system of copying memory from a source processor to a target processor by duplicating memory writes. At least some of the exemplary embodiments may be a method comprising stopping execution of a user program on a target processor (the target processor coupled to a first memory), continuing to execute a duplicate copy of the user program on a source processor (the source processor coupled to a second memory and generating writes to the second memory), duplicating memory writes of the source processor and duplicating writes by input/output adapters to create a stream of duplicate memory writes, and applying the duplicated memory writes to the first memory.
摘要翻译：通过复制存储器写入将存储器从源处理器复制到目标处理器的方法和系统。示例性实施例中的至少一些可以是包括在目标处理器（耦合到第一存储器的目标处理器）上停止执行用户程序的方法，继续在源处理器上执行用户程序的副本（源处理器耦合到第二存储器并且产生对第二存储器的写入），复制源处理器的存储器写入并且通过输入/输出适配器复制写入以创建重复存储器写入流，以及将复制的存储器写入应用于第一存储器。

8. 发明授权

US07426614B2 Method and system of executing duplicate copies of a program in lock step 有权
标题翻译：在锁定步骤中执行程序的副本的方法和系统
公开(公告)号：US07426614B2
公开(公告)日：2008-09-16
申请号：US11347642
申请日：2006-02-03
申请人： William F. Bruckert , Mihai Damian , James S. Klecka , Peter A. Reynolds , Dale E. Southgate
发明人： William F. Bruckert , Mihai Damian , James S. Klecka , Peter A. Reynolds , Dale E. Southgate
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0842 , G06F9/321 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F12/0804
摘要： A method and system of executing duplicate copies of a program in lock step. Some illustrative embodiments are a computer system comprising a first processor executing a program, a second processor executing a duplicate copy of the program (the first processor and second processor executing their respective programs in lock step), a logic device coupled to the processors, and a shared device coupled to the processors through the logic device. The first processor presents to the logic device a first operation involving the shared device, and the second processor does not present an operation, or presents an operation that does not match the first operation. The logic device obtains a second operation from the second processor that matches the first operation, and wherein a single operation that matches the first and second operations is presented to the shared device.
摘要翻译：在锁定步骤中执行程序的副本的方法和系统。一些说明性实施例是包括执行程序的第一处理器，执行程序的副本的第二处理器（第一处理器和第二处理器在锁定步骤中执行它们各自的程序）的计算机系统，耦合到处理器的逻辑设备，以及通过逻辑设备耦合到处理器的共享设备。第一处理器向逻辑设备呈现涉及共享设备的第一操作，并且第二处理器不呈现操作，或呈现与第一操作不匹配的操作。逻辑设备从第二处理器获得与第一操作匹配的第二操作，并且其中将与第一操作和第二操作匹配的单个操作呈现给共享设备。

9. 发明授权

US06948092B2 System recovery from errors for processor and associated components 失效
标题翻译：系统从处理器和相关组件的错误中恢复
公开(公告)号：US06948092B2
公开(公告)日：2005-09-20
申请号：US10061435
申请日：2002-01-31
申请人： Thomas J. Kondo , James S. Klecka , Robert L. Jardine , William P. Bunton , Graham B. Stott
发明人： Thomas J. Kondo , James S. Klecka , Robert L. Jardine , William P. Bunton , Graham B. Stott
IPC分类号： G06F11/14 , G06F11/16 , G06F11/00
CPC分类号： G06F11/1441 , G06F11/1641 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/1679 , G06F11/1683 , G06F11/1695
摘要： A computer system includes a primary processor and a secondary processor running in lockstep. The lockstep may or may not be synchronous. Errors occurring in the primary processor or the secondary processor are reported to an error-handling module. If the error is a recoverable error, the state of one of the processors is saved and the processors are restarted using the saved state. In addition to the reporting of errors from the processors, cross checking of the operation of the processors is performed to detect a divergence in the operation of the processors. If the divergence is reported to be due to a recoverable error, the state of the one of the processors is saved and the processors are restarted using the saved state. Procedures are also disclosed to ensure that data corruption does not propagate onto an associated network, and to ensure that the system is not lost as a network resource during processor restart.
摘要翻译：计算机系统包括主处理器和处于锁定状态的辅助处理器。锁定可以是或可以不是同步的。在主处理器或辅助处理器中发生的错误报告给错误处理模块。如果错误是可恢复的错误，则会保存其中一个处理器的状态，并使用保存的状态重新启动处理器。除了报告来自处理器的错误之外，执行处理器的操作的交叉检查以检测处理器的操作的分歧。如果报告差异是由于可恢复的错误，则保存一个处理器的状态，并使用保存的状态重新启动处理器。还披露了程序以确保数据损坏不会传播到关联的网络上，并确保在处理器重新启动期间系统不会作为网络资源丢失。

10. 发明授权

US5574849A Synchronized data transmission between elements of a processing system 失效
标题翻译：处理系统的元素之间的同步数据传输
公开(公告)号：US5574849A
公开(公告)日：1996-11-12
申请号：US482628
申请日：1995-06-07
申请人： David P. Sonnier , Wiliam P. Bunton , Richard W. Cutts, Jr. , James S. Klecka , John C. Krause , William J. Watson , Linda E. Zalzala
发明人： David P. Sonnier , Wiliam P. Bunton , Richard W. Cutts, Jr. , James S. Klecka , John C. Krause , William J. Watson , Linda E. Zalzala
IPC分类号： G06F11/18 , G01R31/317 , G01R31/3185 , G06F1/12 , G06F9/52 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F11/273 , G06F12/08 , G06F12/14 , G06F12/16 , G06F13/00 , H04L12/56 , H04L29/14 , G01R31/28
CPC分类号： G01R31/31727 , G06F1/12 , G06F11/10 , G06F11/1604 , G06F11/1633 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/1679 , G06F11/1687 , G06F12/0815 , G06F12/1483 , H04L47/10 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L69/40 , G01R31/318533 , G06F11/004 , G06F11/1044 , G06F11/167 , G06F11/1683 , G06F11/1695 , G06F11/20 , G06F11/2043 , G06F11/2097 , G06F11/2736 , G06F2201/845 , H04L12/56
摘要： Two identical streams of multi-bit symbols are received by a pair of storage elements, each having multiple locations and first and second pointer counters respectively identifying the locations at which received symbols are stored and from which stored symbols are retrieved. The storage elements are synchronized by providing each with a SYNC symbol that, when detected, causes the pointer counters to be placed in a predetermined (reset) state on one transition of a SYNC clock signal, releasing the pointer counters at the same time on a following transition of the SYNC clock signal.
摘要翻译：两个相同的多比特符号流由一对存储元件接收，每个存储元件具有多个位置，第一和第二指针计数器分别标识存储接收符号的位置，并从中检索存储的符号。存储元件通过为每个SYNC符号提供同步，当检测到SYNC符号时，在SYNC时钟信号的一个转换上使指针计数器处于预定（复位）状态，同时在一个在SYNC时钟信号转换之后。

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