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11. 发明申请

US20060003572A1 Method for improving a semiconductor device delamination resistance 有权
标题翻译：提高半导体器件耐分层性的方法
公开(公告)号：US20060003572A1
公开(公告)日：2006-01-05
申请号：US10884719
申请日：2004-07-03
申请人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
发明人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53295 , H01L21/76801 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/3135 , H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.
摘要翻译：具有改进的分层耐受性的半导体器件及其形成方法包括提供包含具有最上蚀刻停止层的金属化层的半导体晶片的方法; 在所述蚀刻停止层上形成至少一个附着促进层; 以及在所述至少一个附着促进层上形成金属间电介质（IMD）层。

12. 发明申请

US20110081758A1 Semiconductor device including I/O oxide nitrided core oxide on substrate, and method of manufacture 有权
标题翻译：在衬底上包括I / O氧化物氮化核心氧化物的半导体器件及其制造方法
公开(公告)号：US20110081758A1
公开(公告)日：2011-04-07
申请号：US12923889
申请日：2010-10-13
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , H01L27/088 , Y10S438/981
摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要翻译：半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的核心区域和用于外围电路的外围区域。半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物，以及I / O氧化物上的第二多晶硅图案。

13. 发明授权

US07247571B2 Method for planarizing semiconductor structures 有权
公开(公告)号：US07247571B2
公开(公告)日：2007-07-24
申请号：US11226979
申请日：2005-09-15
申请人： Ying-Tsung Chen , Yung-Cheng Lu , Zhen-Cheng Wu , Pi-Tsung Chen
发明人： Ying-Tsung Chen , Yung-Cheng Lu , Zhen-Cheng Wu , Pi-Tsung Chen
IPC分类号： H01L21/311
CPC分类号： H01L21/31053 , H01L22/20
摘要： A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density, is provided. A first dielectric layer is formed above the semiconductor for covering the trenches in the first and second areas. A first chemical mechanical polishing is performed on the first dielectric layer using a predetermined type of slurry for reducing a thickness thereof. The first dielectric layer is then rinsed. A second chemical mechanical polishing is performed on the first dielectric layer using the predetermined type of slurry for further removing the first dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.

14. 发明申请

US20070096326A1 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070096326A1
公开(公告)日：2007-05-03
申请号：US11261200
申请日：2005-10-28
申请人： Hui-Lin Chang , Yung-Cheng Lu , Chung-Chi Ko , Pi-Tsung Chen , Shau-Lin Shue , Chien-Hsueh Shih , Hung-Wen Su , Ming-Hsing Tsai
发明人： Hui-Lin Chang , Yung-Cheng Lu , Chung-Chi Ko , Pi-Tsung Chen , Shau-Lin Shue , Chien-Hsueh Shih , Hung-Wen Su , Ming-Hsing Tsai
IPC分类号： H01L23/48
CPC分类号： H01L23/53276 , H01L21/76849 , H01L21/76852 , H01L21/76879 , H01L21/76885 , H01L23/5226 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M1, wherein M1 is selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.
摘要翻译：半导体器件及其制造方法。这些器件包括衬底，催化剂层，第二介电层和碳纳米管（CNT）。衬底包括具有嵌入其中的电极的上覆的第一介电层。催化剂层覆盖电极和第一介电层，并且基本上包括Co和M 1，其中M 1选自W，P，B，Bi ，Ni及其组合。第二电介质层覆盖在催化剂层上并且包括露出催化剂层的部分的开口。碳纳米管（CNT）设置在暴露的催化剂层上并电连接电极。

15. 发明申请

US20070013009A1 Semiconductor device including I/O oxide and nitrided core oxide on substrate, and method of manufacture 有权
标题翻译：在衬底上包括I / O氧化物和氮化核心氧化物的半导体器件及其制造方法
公开(公告)号：US20070013009A1
公开(公告)日：2007-01-18
申请号：US11181915
申请日：2005-07-15
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
IPC分类号： H01L29/78 , H01L21/8234
CPC分类号： H01L21/823462 , H01L27/088 , Y10S438/981
摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要翻译：半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的核心区域和用于外围电路的外围区域。半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物，以及I / O氧化物上的第二多晶硅图案。

16. 发明授权

US08084328B2 Semiconductor device including I/O oxide nitrided core oxide on substrate 有权
标题翻译：在衬底上包括I / O氧化物氮化核心氧化物的半导体器件
公开(公告)号：US08084328B2
公开(公告)日：2011-12-27
申请号：US12923889
申请日：2010-10-13
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
IPC分类号： H01I21/8234
CPC分类号： H01L21/823462 , H01L27/088 , Y10S438/981
摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要翻译：半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的芯区域和用于外围电路的外围区域。半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物，以及I / O氧化物上的第二多晶硅图案。

17. 发明申请

US20070054494A1 Method for planarizing semiconductor structures 有权
标题翻译：半导体结构平面化方法
公开(公告)号：US20070054494A1
公开(公告)日：2007-03-08
申请号：US11226979
申请日：2005-09-15
申请人： Ying-Tsung Chen , Yung-Cheng Lu , Zhen-Cheng Wu , Pi-Tsung Chen
发明人： Ying-Tsung Chen , Yung-Cheng Lu , Zhen-Cheng Wu , Pi-Tsung Chen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31053 , H01L22/20
摘要： A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density, is provided. A first dielectric layer is formed above the semiconductor for covering the trenches in the first and second areas. A first chemical mechanical polishing is performed on the first dielectric layer using a predetermined type of slurry for reducing a thickness thereof. The first dielectric layer is then rinsed. A second chemical mechanical polishing is performed on the first dielectric layer using the predetermined type of slurry for further removing the first dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.
摘要翻译：公开了一种用于平面化半导体结构的方法。提供具有第一区域的半导体衬底，其中以第一图案密度形成一个或多个沟槽，以及第二区域，其中以比第一图案密度低的第二图案密度形成一个或多个沟槽。第一介电层形成在半导体上方，用于覆盖第一和第二区域中的沟槽。使用用于减小其厚度的预定类型的浆料在第一介电层上进行第一化学机械抛光。然后冲洗第一介电层。使用预定类型的浆料在第一介电层上进行第二化学机械抛光，用于进一步去除沟槽外的第一介电层，从而降低第一和第二区域的表面之间的台阶高度变化。

18. 发明申请

US20060125102A1 Back end of line integration scheme 审中-公开
标题翻译：后端整合方案
公开(公告)号：US20060125102A1
公开(公告)日：2006-06-15
申请号：US11012406
申请日：2004-12-15
申请人： Zhen-Cheng Wu , Ying-Tsung Chen , Pi-Tsung Chen , Yung-Cheng Lu
发明人： Zhen-Cheng Wu , Ying-Tsung Chen , Pi-Tsung Chen , Yung-Cheng Lu
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/7682 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure comprises: a first inter-layer dielectric (ILD) over a substrate; a first metal layer; a plurality of second ILDs over the first ILD; and a plurality of second metal layers, each of the second metal layers is over one of the second ILDs. The first ILD is not cured. It has a k value of between about 2.5 and about 3.0, a pore size of smaller than about 10 Å, and a hardness of greater than about 1.5 Gpa. The second ILDs are cured therefore having lower k values of smaller than about 2.5, pore sizes of greater than about 10 Å, and hardness of smaller than about 1.5 Gpa. The semiconductor structure has reduced plasma charge damage from plasma curing.
摘要翻译：半导体结构包括：在衬底上的第一层间电介质（ILD）; 第一金属层; 在第一ILD上的多个第二ILD; 以及多个第二金属层，每个第二金属层位于第二ILD之一上。第一个ILD没有治愈。其k值为约2.5至约3.0，孔径小于约10埃，硬度大于约1.5Gpa。因此，第二ILD被固化，因此具有小于约2.5，小于约10埃的孔径和小于约1.5Gpa的硬度的较低k值。半导体结构降低了等离子体固化所产生的等离子体电荷损伤。

19. 发明申请

US20060027924A1 Metallization layers for crack prevention and reduced capacitance 审中-公开
标题翻译：用于防裂和减少电容的金属化层
公开(公告)号：US20060027924A1
公开(公告)日：2006-02-09
申请号：US10910479
申请日：2004-08-03
申请人： Pi-Tsung Chen , Yung-Cheng Lu , Syun-Ming Jang
发明人： Pi-Tsung Chen , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L23/52
CPC分类号： H01L21/76829 , H01L21/288 , H01L21/76807 , H01L21/76832 , H01L21/76849
摘要： A semiconductor device and method for forming the device wherein the device includes a substrate; a dielectric insulating layer formed overlying the substrate; a metal filled dual damascene structure formed in the dielectric insulating layer, wherein the metal filled dual damascene structure includes a via portion and a trench portion; and at least one intervening dielectric layer in compressive stress formed in the dielectric insulating layer and disposed at a level adjacent to at least one of the via portion and the trench portion of the metal filled dual damascene structure.
摘要翻译：一种用于形成该器件的半导体器件和方法，其中所述器件包括衬底; 覆盖所述基板的介电绝缘层; 形成在介电绝缘层中的金属填充双镶嵌结构，其中金属填充的双镶嵌结构包括通孔部分和沟槽部分; 以及形成在介电绝缘层中并且设置在与金属填充的双镶嵌结构的至少一个通孔部分和沟槽部分相邻的水平处的压缩应力中的至少一个中间介电层。

20. 发明申请

US20110197168A1 DECOMPOSING INTEGRATED CIRCUIT LAYOUT 有权
标题翻译：分解集成电路布局
公开(公告)号：US20110197168A1
公开(公告)日：2011-08-11
申请号：US12702591
申请日：2010-02-09
申请人： Pi-Tsung Chen , Ming-Hui Chih , Ken-Hsien Hsieh , Wei-Long Wang , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau , Wen-Ju Yang , Gwan Sin Chang , Yung-Sung Yen
发明人： Pi-Tsung Chen , Ming-Hui Chih , Ken-Hsien Hsieh , Wei-Long Wang , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau , Wen-Ju Yang , Gwan Sin Chang , Yung-Sung Yen
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.
摘要翻译：本发明的各种实施例提供了确保集成电路的布局是可分割的技术。在方法实施例中，在具有布局库作为输入的客户站点中生成布局，其中库提供已经被验证为可以吐出并且可以被使用的示例性布局以及可能引起冲突的布局。还提供了实时奇数周期检查器，其中检查器在布局生成期间出现时实时地识别冲突区域和奇数周期。为了减少各种设备的存储器使用布局可以被分离，使得可以针对冲突来检查每个单独布局或少量布局而不是用于整个应用电路的大布局。一旦布局在客户现场准备就绪，就将其发送到代工厂，将其分解成两个面具并进行录制。还公开了其他实施例。

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