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    • 13. 发明申请
    • TRAIN SPEED CONTROL APPARATUS AND TRAIN SPEED CONTROL METHOD
    • 火车速度控制装置和火车速度控制方法
    • US20130006452A1
    • 2013-01-03
    • US13634307
    • 2010-04-28
    • Masamichi Takagi
    • Masamichi Takagi
    • B60L15/40
    • B60L15/40B60L9/00B60L15/20B60L2200/26Y02T10/72Y02T10/7275
    • To stop a train at a desired target stop position without outputting excessive brake by outputting an appropriate braking instruction in accordance with a running condition of the train. An on-train computing device causes an acceleration estimating unit to determine the presence/absence of a current acceleration of a train and to estimate the current acceleration based on train-car information obtained from a train-car performance manager unit, and causes a profile calculating unit to generate a braking instruction profile based on a presumption that the train is running at the current acceleration when the train is in an accelerating condition, and to generate the braking instruction profile based on a presumption that there is no acceleration applied to a train car of the train by a propulsion control of the train car itself when the train is in a coasting condition.
    • 通过根据列车的行驶状态输出适当的制动指令,将列车停在期望的目标停止位置而不输出过大的制动。 列车计算装置使加速度估计单元确定列车的当前加速度的存在/不存在,并且基于从列车车辆性能管理器单元获得的列车信息来估计当前加速度,并且使轮廓 计算单元,基于当列车处于加速状态时以当前加速度行驶的推测,生成制动指令轮廓,并且基于对列车没有加速度的推定生成制动指令轮廓 火车的汽车在火车处于滑行状态时,通过火车车辆的推进控制。
    • 14. 发明授权
    • Apparatus and method for performing a screening test of semiconductor integrated circuits
    • 用于进行半导体集成电路的屏蔽测试的装置和方法
    • US08301936B2
    • 2012-10-30
    • US12447524
    • 2007-10-17
    • Hiroaki InoueMasamichi TakagiMasayuki Mizuno
    • Hiroaki InoueMasamichi TakagiMasayuki Mizuno
    • G06F11/00
    • G06F11/277
    • An apparatus for performing a screening test of a semiconductor integrated circuit is disclosed, the semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, and the processors being programmatically operable. The apparatus for performing a screening test of a semiconductor integrated circuit comprises: an instruction/data signal synchronization circuit for synchronizing the supplying of instructions to said respective processors and for synchronizing the supplying of data to said respective processors; and a trace comparison circuit for comparing instruction execution information that are output from the respective processors to determine whether or not any of said processors has output different instruction execution information.
    • 公开了一种用于执行半导体集成电路的屏蔽测试的装置,所述半导体集成电路包括多个处理器,每个处理器具有用于指令执行信息的输出信号,并且所述处理器可编程地可操作。 用于执行半导体集成电路的屏蔽测试的装置包括:指令/数据信号同步电路,用于将指令的提供同步到所述各个处理器并用于同步向所述各个处理器提供数据; 以及跟踪比较电路,用于比较从各个处理器输出的指令执行信息,以确定所述处理器中的任何一个是否输出了不同的指令执行信息。
    • 15. 发明授权
    • Semiconductor integrated circuit and testing method therefor
    • 半导体集成电路及其测试方法
    • US08248073B2
    • 2012-08-21
    • US12529458
    • 2008-02-19
    • Hiroaki InoueMasamichi Takagi
    • Hiroaki InoueMasamichi Takagi
    • G01V3/00
    • G01R31/31724G01R31/31723G01R31/318536G06F11/2236
    • A semiconductor integrated circuit comprises a plurality of cores (99) connected with an inter-connection network (1000) and a test controller (500) which is connected with the inter-connection network (1000) and which issues a test control request associated with the test of the core (99) via the inter-connection network (1000). The inter-connection network (1000) is constituted of a plurality of adapters (3000) which serve as connection interfaces of the plurality of cores (99) and the test controller (500), respectively, and a plurality of routers (2000) which connect the plurality of adapters (3000). The adapters (3000) connected with the core (99) comprise a core testing unit for vicariously testing core (99) connected to itself based on the test control request received from the test controller (500) via the inter-connection network (1000).
    • 半导体集成电路包括与互连网络(1000)连接的多个核(99)和与所述互连网络(1000)连接的测试控制器(500),并且发出与 通过互连网络(1000)对核心(99)进行测试。 互连网络(1000)由分别用作多个核(99)和测试控制器(500)的连接接口的多个适配器(3000)和多个路由器(2000)组成,多个路由器 连接多个适配器(3000)。 与核心(99)连接的适配器(3000)包括核心测试单元,用于根据从测试控制器(500)经由互连网络(1000)接收的测试控制请求代替连接到其自身的核心(99) 。
    • 17. 发明申请
    • INFORMATION PROCESSING DEVICE AND FAILURE CONCEALING METHOD THEREFOR
    • 信息处理设备和故障隐患方法
    • US20090240980A1
    • 2009-09-24
    • US12441289
    • 2007-09-13
    • Hiroaki InoueMasamichi TakagiMasayuki Mizuno
    • Hiroaki InoueMasamichi TakagiMasayuki Mizuno
    • G06F11/20
    • G06F11/2043G06F11/2023G06F11/2025G06F11/203G06F11/2033G06F11/2035
    • An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit.
    • 信息处理装置包括操作系统和执行环境操作的多个处理单元以及由多个处理单元共享的共享外围设备。 信息处理装置设置有用于隐藏处理单元中发生的故障的故障隐藏装置。 故障隐藏装置决定将作为故障处理单元的替代物的替代处理单元,使得在故障处理单元上操作的OS和执行环境将在替代处理单元上操作,切换OS和执行环境, 在故障处理单元上操作,使得它们在替代处理单元上操作,并且切换由故障处理单元使用的共享资源,使得它可用于替代处理单元。