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    • 3. 发明授权
    • Information processing device and failure concealing method therefor
    • 信息处理装置及其故障隐藏方法
    • US08108719B2
    • 2012-01-31
    • US12441289
    • 2007-09-13
    • Hiroaki InoueMasamichi TakagiMasayuki Mizuno
    • Hiroaki InoueMasamichi TakagiMasayuki Mizuno
    • G06F11/00
    • G06F11/2043G06F11/2023G06F11/2025G06F11/203G06F11/2033G06F11/2035
    • An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit.
    • 信息处理装置包括操作系统和执行环境操作的多个处理单元以及由多个处理单元共享的共享外围设备。 信息处理装置设置有用于隐藏处理单元中发生的故障的故障隐藏装置。 故障隐藏装置决定将作为故障处理单元的替代物的替代处理单元,使得在故障处理单元上操作的OS和执行环境将在替代处理单元上操作,切换OS和执行环境, 在故障处理单元上操作,使得它们在替代处理单元上操作,并且切换由故障处理单元使用的共享资源,使得它可用于替代处理单元。
    • 4. 发明申请
    • APPARATUS AND METHOD FOR PERFORMING A SCREENING TEST OF SEMICONDUCTOR INTEGRATED CIRCUITS
    • 用于执行半导体集成电路的屏幕测试的装置和方法
    • US20100077259A1
    • 2010-03-25
    • US12447524
    • 2007-10-17
    • Hiroaki InoueMasamichi TakagiMasayuki Mizuno
    • Hiroaki InoueMasamichi TakagiMasayuki Mizuno
    • G06F9/30G06F11/07
    • G06F11/277
    • An apparatus for performing a screening test of a semiconductor integrated circuit is disclosed, the semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, and the processors being programmatically operable. The apparatus for performing a screening test of a semiconductor integrated circuit comprises: an instruction/data signal synchronization circuit for synchronizing the supplying of instructions to said respective processors and for synchronizing the supplying of data to said respective processors; and a trace comparison circuit for comparing instruction execution information that are output from the respective processors to determine whether or not any of said processors has output different instruction execution information.
    • 公开了一种用于执行半导体集成电路的屏蔽测试的装置,所述半导体集成电路包括多个处理器,每个处理器具有用于指令执行信息的输出信号,并且所述处理器可编程地可操作。 用于执行半导体集成电路的屏蔽测试的装置包括:指令/数据信号同步电路,用于将指令的提供同步到所述各个处理器并用于同步向所述各个处理器提供数据; 以及跟踪比较电路,用于比较从各个处理器输出的指令执行信息,以确定所述处理器中的任何一个是否输出了不同的指令执行信息。
    • 5. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREFOR
    • 半导体集成电路及其测试方法
    • US20100070802A1
    • 2010-03-18
    • US12529458
    • 2008-02-19
    • Hiroaki InoueMasamichi Takagi
    • Hiroaki InoueMasamichi Takagi
    • G06F11/273
    • G01R31/31724G01R31/31723G01R31/318536G06F11/2236
    • A semiconductor integrated circuit comprises a plurality of cores (99) connected with an inter-connection network (1000) and a test controller (500) which is connected with the inter-connection network (1000) and which issues a test control request associated with the test of the core (99) via the inter-connection network (1000). The inter-connection network (1000) is constituted of a plurality of adapters (3000) which serve as connection interfaces of the plurality of cores (99) and the test controller (500), respectively, and a plurality of routers (2000) which connect the plurality of adapters (3000). The adapters (3000) connected with the core (99) comprise a core testing unit for vicariously testing core (99) connected to itself based on the test control request received from the test controller (500) via the inter-connection network (1000).
    • 半导体集成电路包括与互连网络(1000)连接的多个核(99)和与所述互连网络(1000)连接的测试控制器(500),并且发出与 通过互连网络(1000)对核心(99)进行测试。 互连网络(1000)由分别用作多个核(99)和测试控制器(500)的连接接口的多个适配器(3000)和多个路由器(2000)组成,多个路由器 连接多个适配器(3000)。 与核心(99)连接的适配器(3000)包括核心测试单元,用于根据从测试控制器(500)经由互连网络(1000)接收的测试控制请求代替连接到其自身的核心(99) 。
    • 9. 发明授权
    • Escherichia coli Candida maltosa Saccharomyces cerevisiae shuttle
vectors and method for making
    • 大肠杆菌麦芽糖酵母(Saccharomyces cerevisiae)梭菌载体及其制备方法
    • US4879230A
    • 1989-11-07
    • US813193
    • 1985-12-24
    • Masamichi TakagiKeiji YanoIchiro ShibuyaMinoru Morikawa
    • Masamichi TakagiKeiji YanoIchiro ShibuyaMinoru Morikawa
    • C12N15/81
    • C12N15/81
    • The present invention relates to plasmids whose hosts can be Escherichia coli and some kinds of yeasts, namely, shuttle vectors, as well as to processes for producing said plasmids. There are provided in the present invention (1) plasmids containing an autonomously replicating sequence of Candida maltosa, Leu 2 gene derived from Saccharomyces cerevisiae and an ampicillin resistance gene and (2) plasmids further containing a tetracycline resistance gene as well as the genes described in (1).The plasmids (shuttle vectors) of the present invention can be utilized as follows. A useful foreign gene is inserted into plasmids of the present invention; using the resulting new plasid, Escherichia coli is transformed and cultured in order to obtain the plasmid in a large amount; and using this plasmid, Saccharomyces cerevisiae or Candida maltosa as a host is allowed to produce useful substances such as hormones and enzymes on a large scale.
    • 本发明涉及其宿主可以是大肠杆菌和一些种类的酵母的质粒,即穿梭载体,以及生产所述质粒的方法。 在本发明中提供了(1)含有自愿复制的假丝酵母(Candida maltosa)的质粒,来源于酿酒酵母的Leu 2基因和氨苄青霉素抗性基因的质粒和(2)进一步含有四环素抗性基因的质粒以及描述于 (1)。 本发明的质粒(穿梭载体)可以如下使用。 将有用的外源基因插入本发明的质粒中; 使用所得的新的质粒,转化和培养大肠杆菌以获得大量的质粒; 使用该质粒,可以将酿酒酵母或麦芽假丝酵母作为宿主大量产生有用的物质如激素和酶。
    • 10. 发明授权
    • Router, information processing device having said router, and packet routing method
    • 路由器,具有所述路由器的信息处理设备和分组路由方法
    • US08638665B2
    • 2014-01-28
    • US12935035
    • 2009-04-30
    • Masamichi TakagiSunao Torii
    • Masamichi TakagiSunao Torii
    • G06F11/00
    • H04L45/00H04L45/60H04L49/109H04L49/1546H04L49/251
    • A router includes: a flit arrival time management section that records flit arrival time which is the time at which the packet is received for the first time, transmission interval of the packet which are acquired from a control packet transmitted prior to the first transmission of a packet and input and output channels of the control packet and requires a crossbar section for an output channel from which the packet is supposed to be output before the flit arrival time; a switch assignment section that performs arbitration on the output channel request and performs input/output connection relationship setting processing; and a switch assignment verification section that verifies whether a result of the input/output connection relationship setting processing coincides with the actual routing of the packet. The cross bar section performs switching of the arriving packet using a result of the input/output connection relationship processing.
    • 路由器包括:飞行到达时间管理部,其记录作为第一次接收分组的时间的飞行到达时间,从在第一次发送之前发送的控制分组获取的分组的发送间隔 分组和控制分组的输入和输出通道,并且需要用于输出通道的横截面部分,在该输出通道之前,应该在该飞行器到达时间之前输出该分组; 开关分配单元,对所述输出通道请求进行仲裁,并进行输入/输出连接关系设定处理; 以及开关分配验证部,其验证输入/输出连接关系设置处理的结果是否与分组的实际路由一致。 横杆部分使用输入/输出连接关系处理的结果来执行到达的分组的切换。