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1. 发明申请

US20100100886A1 TASK GROUP ALLOCATING METHOD, TASK GROUP ALLOCATING DEVICE, TASK GROUP ALLOCATING PROGRAM, PROCESSOR AND COMPUTER 有权
标题翻译：任务组分配方法，任务组分配设备，任务组分配程序，处理器和计算机
公开(公告)号：US20100100886A1
公开(公告)日：2010-04-22
申请号：US12529367
申请日：2008-02-05
申请人： Masamichi Takagi , Masayuki Mizuno , Hiroaki Inoue
发明人： Masamichi Takagi , Masayuki Mizuno , Hiroaki Inoue
IPC分类号： G06F9/50
CPC分类号： G06F9/5027 , G06F11/1428 , G06F11/3419 , G06F11/3433 , G06F2209/483 , G06F2209/501
摘要： Even if a multiprocessor includes an uneven performance core, an inoperative core or a core that does not satisfy such a performance as designed but if the contrivance of task allocation can satisfy the requirement of an application to be executed, the multiple processors are shipped. In a task group allocation method for allocating, to a processor having a plurality of cores, task groups included in an application for the processor to execute, a calculation section measures performances and disposition patterns of the cores, generates a restricting condition associating the measured performances and disposition patterns of the cores with information indicating whether the application can be executed, and, with reference to the restricting condition, reallocates to the cores, the task groups that have previously been allocated to the cores.
摘要翻译：即使多处理器包括不均衡的性能核心，不能满足设计性能的不工作核心或核心，但如果任务分配的设计能够满足执行应用程序的要求，则会发送多个处理器。在用于将具有多个核心的处理器分配给应用程序中的处理器执行的任务组的任务组分配方法中，计算部分测量核心的性能和配置模式，产生将测量性能以及具有指示是否可以执行应用的信息的核心的配置模式，并且参考限制条件将已经分配给核心的任务组重新分配给核心。

2. 发明授权

US08140912B2 Semiconductor integrated circuits and method of detecting faults of processors 失效
标题翻译：半导体集成电路和检测处理器故障的方法
公开(公告)号：US08140912B2
公开(公告)日：2012-03-20
申请号：US12447512
申请日：2007-10-19
申请人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
发明人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
IPC分类号： G06F11/00
CPC分类号： G06F11/0721 , G06F11/0751 , G06F11/2236
摘要： A semiconductor integrated circuit comprising a processor having an output signal of instruction log information and being operable in a program in memory is disclosed. The semiconductor integrated circuit comprises trace determination circuit for comparing an instruction code that corresponds to the instruction log information from a processor with an instruction code that is read from the memory to detect faults.
摘要翻译：公开了一种半导体集成电路，其包括具有指令日志信息的输出信号并且可在存储器中的程序中操作的处理器。半导体集成电路包括跟踪确定电路，用于将来自处理器的与指令日志信息相对应的指令代码与从存储器读取的指令代码进行比较以检测故障。

3. 发明授权

US08429663B2 Allocating task groups to processor cores based on number of task allocated per core, tolerable execution time, distance between cores, core coordinates, performance and disposition pattern 有权
标题翻译：根据每个核心分配的任务数量，允许的执行时间，核心距离，核心坐标，性能和配置模式，将任务组分配到处理器核心
公开(公告)号：US08429663B2
公开(公告)日：2013-04-23
申请号：US12529367
申请日：2008-02-05
申请人： Masamichi Takagi , Masayuki Mizuno , Hiroaki Inoue
发明人： Masamichi Takagi , Masayuki Mizuno , Hiroaki Inoue
IPC分类号： G06F9/50
CPC分类号： G06F9/5027 , G06F11/1428 , G06F11/3419 , G06F11/3433 , G06F2209/483 , G06F2209/501
摘要： Even if a multiprocessor includes an uneven performance core, an inoperative core or a core that does not satisfy such a performance as designed but if the contrivance of task allocation can satisfy the requirement of an application to be executed, the multiple processors are shipped. In a task group allocation method for allocating, to a processor having a plurality of cores, task groups included in an application for the processor to execute, a calculation section measures performances and disposition patterns of the cores, generates a restricting condition associating the measured performances and disposition patterns of the cores with information indicating whether the application can be executed, and, with reference to the restricting condition, reallocates to the cores, the task groups that have previously been allocated to the cores.
摘要翻译：即使多处理器包括不均衡的性能核心，不能满足设计性能的不工作核心或核心，但是如果任务分配的设计能够满足执行应用程序的要求，则会发送多个处理器。在用于将具有多个核心的处理器分配给应用程序中的处理器执行的任务组的任务组分配方法中，计算部分测量核心的性能和配置模式，产生将测量性能以及具有指示是否可以执行应用的信息的核心的配置模式，并且参考限制条件将已经分配给核心的任务组重新分配给核心。

4. 发明授权

US08301936B2 Apparatus and method for performing a screening test of semiconductor integrated circuits 失效
标题翻译：用于进行半导体集成电路的屏蔽测试的装置和方法
公开(公告)号：US08301936B2
公开(公告)日：2012-10-30
申请号：US12447524
申请日：2007-10-17
申请人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
发明人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
IPC分类号： G06F11/00
CPC分类号： G06F11/277
摘要： An apparatus for performing a screening test of a semiconductor integrated circuit is disclosed, the semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, and the processors being programmatically operable. The apparatus for performing a screening test of a semiconductor integrated circuit comprises: an instruction/data signal synchronization circuit for synchronizing the supplying of instructions to said respective processors and for synchronizing the supplying of data to said respective processors; and a trace comparison circuit for comparing instruction execution information that are output from the respective processors to determine whether or not any of said processors has output different instruction execution information.
摘要翻译：公开了一种用于执行半导体集成电路的屏蔽测试的装置，所述半导体集成电路包括多个处理器，每个处理器具有用于指令执行信息的输出信号，并且所述处理器可编程地可操作。用于执行半导体集成电路的屏蔽测试的装置包括：指令/数据信号同步电路，用于将指令的提供同步到所述各个处理器并用于同步向所述各个处理器提供数据; 以及跟踪比较电路，用于比较从各个处理器输出的指令执行信息，以确定所述处理器中的任何一个是否输出了不同的指令执行信息。

5. 发明申请

US20090240980A1 INFORMATION PROCESSING DEVICE AND FAILURE CONCEALING METHOD THEREFOR 失效
标题翻译：信息处理设备和故障隐患方法
公开(公告)号：US20090240980A1
公开(公告)日：2009-09-24
申请号：US12441289
申请日：2007-09-13
申请人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
发明人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
IPC分类号： G06F11/20
CPC分类号： G06F11/2043 , G06F11/2023 , G06F11/2025 , G06F11/203 , G06F11/2033 , G06F11/2035
摘要： An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit.
摘要翻译：信息处理装置包括操作系统和执行环境操作的多个处理单元以及由多个处理单元共享的共享外围设备。信息处理装置设置有用于隐藏处理单元中发生的故障的故障隐藏装置。故障隐藏装置决定将作为故障处理单元的替代物的替代处理单元，使得在故障处理单元上操作的OS和执行环境将在替代处理单元上操作，切换OS和执行环境，在故障处理单元上操作，使得它们在替代处理单元上操作，并且切换由故障处理单元使用的共享资源，使得它可用于替代处理单元。

6. 发明授权

US08108719B2 Information processing device and failure concealing method therefor 失效
标题翻译：信息处理装置及其故障隐藏方法
公开(公告)号：US08108719B2
公开(公告)日：2012-01-31
申请号：US12441289
申请日：2007-09-13
申请人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
发明人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
IPC分类号： G06F11/00
CPC分类号： G06F11/2043 , G06F11/2023 , G06F11/2025 , G06F11/203 , G06F11/2033 , G06F11/2035
摘要： An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit.
摘要翻译：信息处理装置包括操作系统和执行环境操作的多个处理单元以及由多个处理单元共享的共享外围设备。信息处理装置设置有用于隐藏处理单元中发生的故障的故障隐藏装置。故障隐藏装置决定将作为故障处理单元的替代物的替代处理单元，使得在故障处理单元上操作的OS和执行环境将在替代处理单元上操作，切换OS和执行环境，在故障处理单元上操作，使得它们在替代处理单元上操作，并且切换由故障处理单元使用的共享资源，使得它可用于替代处理单元。

7. 发明申请

US20100077259A1 APPARATUS AND METHOD FOR PERFORMING A SCREENING TEST OF SEMICONDUCTOR INTEGRATED CIRCUITS 失效
标题翻译：用于执行半导体集成电路的屏幕测试的装置和方法
公开(公告)号：US20100077259A1
公开(公告)日：2010-03-25
申请号：US12447524
申请日：2007-10-17
申请人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
发明人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
IPC分类号： G06F9/30 , G06F11/07
CPC分类号： G06F11/277
摘要： An apparatus for performing a screening test of a semiconductor integrated circuit is disclosed, the semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, and the processors being programmatically operable. The apparatus for performing a screening test of a semiconductor integrated circuit comprises: an instruction/data signal synchronization circuit for synchronizing the supplying of instructions to said respective processors and for synchronizing the supplying of data to said respective processors; and a trace comparison circuit for comparing instruction execution information that are output from the respective processors to determine whether or not any of said processors has output different instruction execution information.
摘要翻译：公开了一种用于执行半导体集成电路的屏蔽测试的装置，所述半导体集成电路包括多个处理器，每个处理器具有用于指令执行信息的输出信号，并且所述处理器可编程地可操作。用于执行半导体集成电路的屏蔽测试的装置包括：指令/数据信号同步电路，用于将指令的提供同步到所述各个处理器并用于同步向所述各个处理器提供数据; 以及跟踪比较电路，用于比较从各个处理器输出的指令执行信息，以确定所述处理器中的任何一个是否输出了不同的指令执行信息。

8. 发明申请

US20100153784A1 SEMICONDUCTOR INTEGRATED CIRCUITS AND METHOD OF DETECTING FAULTS OF PROCESSORS 失效
标题翻译：半导体集成电路和检测处理器故障的方法
公开(公告)号：US20100153784A1
公开(公告)日：2010-06-17
申请号：US12447512
申请日：2007-10-19
申请人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
发明人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
IPC分类号： G06F11/36 , G06F11/34
CPC分类号： G06F11/0721 , G06F11/0751 , G06F11/2236
摘要： A semiconductor integrated circuit comprising a processor having an output signal of instruction log information and being operable in a program in memory is disclosed. The semiconductor integrated circuit comprises trace determination circuit for comparing an instruction code that corresponds to the instruction log information from a processor with an instruction code that is read from the memory to detect faults.
摘要翻译：公开了一种半导体集成电路，其包括具有指令日志信息的输出信号并且可在存储器中的程序中操作的处理器。半导体集成电路包括跟踪确定电路，用于将来自处理器的与指令日志信息相对应的指令代码与从存储器读取的指令代码进行比较以检测故障。

9. 发明授权

US08412867B2 Semiconductor integrated circuit and filter and informational delivery method using same 有权
标题翻译：半导体集成电路和滤波器及信息传递方法使用相同
公开(公告)号：US08412867B2
公开(公告)日：2013-04-02
申请号：US12663477
申请日：2008-05-30
申请人： Hiroaki Inoue , Masamichi Takagi , Masaki Uekubo , Sunao Torii , Masato Edahiro
发明人： Hiroaki Inoue , Masamichi Takagi , Masaki Uekubo , Sunao Torii , Masato Edahiro
IPC分类号： G06F13/12 , H04L12/56
CPC分类号： G06F15/16 , G06F21/50 , G06F21/577 , H04L29/06
摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.
摘要翻译：本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。适配器保持指示从核心接收到的请求信号的传送条件的传送信息，并且根据传送信息控制从核心接收的请求信号的传送。

10. 发明授权

US08248073B2 Semiconductor integrated circuit and testing method therefor 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US08248073B2
公开(公告)日：2012-08-21
申请号：US12529458
申请日：2008-02-19
申请人： Hiroaki Inoue , Masamichi Takagi
发明人： Hiroaki Inoue , Masamichi Takagi
IPC分类号： G01V3/00
CPC分类号： G01R31/31724 , G01R31/31723 , G01R31/318536 , G06F11/2236
摘要： A semiconductor integrated circuit comprises a plurality of cores (99) connected with an inter-connection network (1000) and a test controller (500) which is connected with the inter-connection network (1000) and which issues a test control request associated with the test of the core (99) via the inter-connection network (1000). The inter-connection network (1000) is constituted of a plurality of adapters (3000) which serve as connection interfaces of the plurality of cores (99) and the test controller (500), respectively, and a plurality of routers (2000) which connect the plurality of adapters (3000). The adapters (3000) connected with the core (99) comprise a core testing unit for vicariously testing core (99) connected to itself based on the test control request received from the test controller (500) via the inter-connection network (1000).
摘要翻译：半导体集成电路包括与互连网络（1000）连接的多个核（99）和与所述互连网络（1000）连接的测试控制器（500），并且发出与通过互连网络（1000）对核心（99）进行测试。互连网络（1000）由分别用作多个核（99）和测试控制器（500）的连接接口的多个适配器（3000）和多个路由器（2000）组成，多个路由器连接多个适配器（3000）。与核心（99）连接的适配器（3000）包括核心测试单元，用于根据从测试控制器（500）经由互连网络（1000）接收的测试控制请求代替连接到其自身的核心（99）。

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