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11. 发明授权

US06465370B1 Low leakage, low capacitance isolation material 失效
标题翻译：低泄漏，低电容隔离材料
公开(公告)号：US06465370B1
公开(公告)日：2002-10-15
申请号：US09105633
申请日：1998-06-26
申请人： Martin Schrems , Rolf-Peter Vollertsen , Joachim Hoepfner
发明人： Martin Schrems , Rolf-Peter Vollertsen , Joachim Hoepfner
IPC分类号： H01L21469
CPC分类号： H01L27/10861 , H01L21/3003 , H01L29/66181 , H01L2924/0002 , Y10S438/918 , H01L2924/00
摘要： A method for reducing a capacitance formed on a silicon substrate includes the step of introducing hydrogen atoms into a portion of said surface to increase the dielectric constant of such portion of the surface increasing the effective thickness of the dielectric material and hence reducing said capacitance. The method includes the step of forming the silicon dioxide layer with a thickness greater than two nanometers. The step of introducing hydrogen includes forming hydrogen atoms in the surface with concentrations of 1017 atoms per cubic centimeter, or greater. In one embodiment the hydrogen atoms are introduced by baking in hydrogen at a temperature of 950° C. to 1100° C. and pressure greater than 100 Torr. A trench capacitor DRAM cell is provided wherein the hydrogen provides a passivation layer to increase the effective capacitance around a collar region and thereby reduce unwanted transistor action.
摘要翻译：减少形成在硅衬底上的电容的方法包括将氢原子引入所述表面的一部分以增加表面部分的介电常数增加介电材料的有效厚度从而减小所述电容的步骤。该方法包括形成厚度大于2纳米的二氧化硅层的步骤。引入氢的步骤包括在表面上形成浓度为1017原子/立方厘米或更大的氢原子。在一个实施方案中，氢原子通过在氢气中在950℃至1100℃的温度和大于100托的压力下进行烘烤而引入。提供了一种沟槽电容器DRAM单元，其中氢提供钝化层以增加环绕区域周围的有效电容，从而减少不需要的晶体管作用。

12. 发明授权

US06265741B1 Trench capacitor with epi buried layer 失效
标题翻译：带Epi埋层的沟槽电容器
公开(公告)号：US06265741B1
公开(公告)日：2001-07-24
申请号：US09056119
申请日：1998-04-06
申请人： Martin Schrems
发明人： Martin Schrems
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L29/945
摘要： A trench capacitor with an epitaxial layer in the lower portion of the trench. The epitaxial layer may be doped to serve as a buried plate.
摘要翻译：沟槽电容器，其在沟槽的下部具有外延层。外延层可以被掺杂以用作掩埋板。

13. 发明授权

US09443759B2 Method for producing a semiconductor device comprising a conductor layer in the semiconductor body and semiconductor body 有权
标题翻译：用于制造半导体器件的方法，该半导体器件包括半导体本体和半导体本体中的导体层
公开(公告)号：US09443759B2
公开(公告)日：2016-09-13
申请号：US14124666
申请日：2012-05-16
申请人： Rainer Minixhofer , Ewald Stückler , Martin Schrems , Günther Koppitsch , Jochen Kraft , Jordi Teva
发明人： Rainer Minixhofer , Ewald Stückler , Martin Schrems , Günther Koppitsch , Jochen Kraft , Jordi Teva
IPC分类号： H01L21/76 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76877 , H01L21/76802 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A cutout (11), which penetrates the semiconductor body, is present in the semiconductor body (1). A conductor layer (6), which is electrically conductively connected to a metal plane (3) on or over the semiconductor body, screens the semiconductor body electrically from the cutout. The conductor layer can be metal, optionally with a barrier layer (6a), or a doped region of the semiconductor body.
摘要翻译：在半导体本体（1）中存在穿过半导体本体的切口（11）。与半导体主体上或上方的金属平面（3）导电连接的导体层（6）从半导体电路屏蔽半导体本体。导体层可以是金属，任选地具有阻挡层（6a）或半导体本体的掺杂区域。

14. 发明申请

US20140191413A1 METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE COMPRISING A CONDUCTOR LAYER IN THE SEMICONDUCTOR BODY AND SEMICONDUCTOR BODY 有权
标题翻译：用于生产在半导体体和半导体体中包含导体层的半导体器件的方法
公开(公告)号：US20140191413A1
公开(公告)日：2014-07-10
申请号：US14124666
申请日：2012-05-16
申请人： Rainer Minixhofer , Ewald Stückler , Martin Schrems , Günther Koppitsch , Jochen Kraft , Jordi Teva
发明人： Rainer Minixhofer , Ewald Stückler , Martin Schrems , Günther Koppitsch , Jochen Kraft , Jordi Teva
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76877 , H01L21/76802 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A cutout (11), which penetrates the semiconductor body, is present in the semiconductor body (1). A conductor layer (6), which is electrically conductively connected to a metal plane (3) on or over the semiconductor body, screens the semiconductor body electrically from the cutout. The conductor layer can be metal, optionally with a barrier layer (6a), or a doped region of the semiconductor body.
摘要翻译：在半导体本体（1）中存在穿过半导体本体的切口（11）。与半导体主体上或上方的金属平面（3）导电连接的导体层（6）从半导体电路屏蔽半导体本体。导体层可以是金属，任选地具有阻挡层（6a）或半导体本体的掺杂区域。

15. 发明授权

US06777303B2 Method for fabricating an insulation collar in a trench capacitor 失效
标题翻译：在沟槽电容器中制造绝缘套环的方法
公开(公告)号：US06777303B2
公开(公告)日：2004-08-17
申请号：US10153045
申请日：2002-05-22
申请人： Martin Schrems , Anke Krasemann , Moritz Haupt , Sabine Steck , Daniel Köhler
发明人： Martin Schrems , Anke Krasemann , Moritz Haupt , Sabine Steck , Daniel Köhler
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L29/66181
摘要： A trench capacitor is formed with an insulation collar. After the formation of the trench, firstly an insulating layer is deposited, from which layer the insulation collar will be subsequently formed. Afterward, the trench is partly filled with a sacrificial filling material and a thin patterning layer is deposited thereon. Spacers are formed from that layer and cover the insulating layer in the upper region of the trench. Afterward, the sacrificial filling material and the insulating layer are completely removed in the lower region of the trench. As a result, the insulation collar is produced in the upper region of the trench.
摘要翻译：沟槽电容器形成有绝缘套环。在形成沟槽之后，首先沉积绝缘层，从该层将形成绝缘套环。之后，沟槽部分地填充有牺牲填充材料，并且在其上沉积薄图案层。间隔由该层形成并覆盖沟槽上部区域中的绝缘层。之后，牺牲填充材料和绝缘层在沟槽的下部区域被完全去除。结果，在沟槽的上部区域中产生绝缘套环。

16. 发明授权

US06750111B2 Method for fabricating a trench capacitor 失效
标题翻译：沟槽电容器的制造方法
公开(公告)号：US06750111B2
公开(公告)日：2004-06-15
申请号：US10390865
申请日：2003-03-17
申请人： Martin Schrems
发明人： Martin Schrems
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L27/10867
摘要： A trench capacitor has an insulation collar that is formed non-conformally in the upper region of a trench in such a way that a layer thickness in an upper section of the insulation collar is greater than a layer thickness in a lower section of the insulation collar. This results in a trench capacitor having improved leakage current properties. A simplified and cost-effective method of fabricating a trench capacitor is also provided.
摘要翻译：沟槽电容器具有绝缘套环，其在沟槽的上部区域中非保形地形成，使得绝缘套环的上部中的层厚度大于绝缘套环下部的层厚度。这导致具有改善的漏电流特性的沟槽电容器。还提供了一种制造沟槽电容器的简化且成本有效的方法。

17. 发明授权

US06677218B2 Method for filling trenches in integrated semiconductor circuits 有权
标题翻译：在集成半导体电路中填充沟槽的方法
公开(公告)号：US06677218B2
公开(公告)日：2004-01-13
申请号：US10210374
申请日：2002-07-31
申请人： Markus Kirchhoff , Martin Schrems
发明人： Markus Kirchhoff , Martin Schrems
IPC分类号： H01L21762
CPC分类号： H01L27/1087 , H01L21/02238 , H01L21/02258 , H01L21/31675 , H01L21/76224
摘要： A method in which a recess is formed in the surface of a semiconductor substrate and a material is grown on the inner wall of the recess, includes the steps of producing an electrically insulating layer on the surface of the substrate outside the recess, and selectively growing the material on the inner wall of the recess as a result of the substrate, as an electrode, being brought into contact with an electrolysis liquid and electrolysis being carried out, during which the insulating layer prevents the material from growing outside the recess. Before the electrolysis is carried out, a reserve material is epitaxially deposited on the inner wall of the recess and, during the electrolysis, the reserve material is converted into the material being grown by electrolysis.
摘要翻译：一种在半导体衬底的表面上形成凹槽并且在凹部的内壁上生长材料的方法包括以下步骤：在凹部外部的衬底表面上制造电绝缘层，并且选择性地生长作为电极的作为电极的基板的内壁上的材料与电解液体接触并进行电解，在此期间绝缘层防止材料在凹部外生长。在进行电解之前，将储备材料外延地沉积在凹槽的内壁上，并且在电解期间，储备材料被转化为通过电解生长的材料。

18. 发明授权

US06580118B2 Non-volatile semiconductor memory cell having a metal oxide dielectric, and method for fabricating the memory cell 有权
标题翻译：具有金属氧化物电介质的非挥发性半导体存储单元及其制造方法
公开(公告)号：US06580118B2
公开(公告)日：2003-06-17
申请号：US10013271
申请日：2001-12-10
申请人： Christoph Ludwig , Martin Schrems
发明人： Christoph Ludwig , Martin Schrems
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/28273
摘要： A non-volatile semiconductor memory cell and an associated method are disclosed, in which a conventional dielectric ONO layer (10) is replaced by a very thin metal oxide layer (6) of WOx and/or TiO2. The high relative dielectric constant of these materials further improves the integration density and the control voltages required for the semiconductor memory cell.
摘要翻译：公开了一种非易失性半导体存储器单元及其相关方法，其中传统的电介质ONO层（10）由非常薄的WO x和/或TiO 2的金属氧化物层（6）代替。这些材料的高相对介电常数进一步提高了半导体存储单元所需的积分密度和控制电压。

19. 发明授权

US06580110B2 Trench capacitor and method for fabricating a trench capacitor 有权
标题翻译：沟槽电容器和制造沟槽电容器的方法
公开(公告)号：US06580110B2
公开(公告)日：2003-06-17
申请号：US09833352
申请日：2001-04-12
申请人： Martin Schrems
发明人： Martin Schrems
IPC分类号： A01L2976
CPC分类号： H01L27/10861 , H01L27/10867
摘要： A trench capacitor has an insulation collar that is formed non-conformally in the upper region of a trench in such a way that a layer thickness in an upper section of the insulation collar is greater than a layer thickness in a lower section of the insulation collar. This results in a trench capacitor having improved leakage current properties. A simplified and cost-effective method of fabricating a trench capacitor is also provided.
摘要翻译：沟槽电容器具有绝缘套环，其在沟槽的上部区域中非保形地形成，使得绝缘套环的上部中的层厚度大于绝缘套环下部的层厚度。这导致具有改善的漏电流特性的沟槽电容器。还提供了一种制造沟槽电容器的简化且成本有效的方法。

20. 发明授权

US06537926B1 Process for improving the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication 有权
标题翻译：用于改善半导体晶片制造中的薄氧化物层的厚度均匀性的方法
公开(公告)号：US06537926B1
公开(公告)日：2003-03-25
申请号：US09638309
申请日：2000-08-14
申请人： Martin Schrems , Helmut Horst Tews
发明人： Martin Schrems , Helmut Horst Tews
IPC分类号： H01L2131
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662
摘要： A two-step progressive thermal oxidation process is provided to improve the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication. A semiconductor wafer, e.g., of silicon, with a surface subject to formation of an oxide layer thereon but which is substantially oxide layer-free, is loaded, e.g., at room temperature, into an oxidation furnace maintained at a low loading temperature, e.g., of 400-600° C., and the wafer temperature is adjusted to a low oxidizing temperature, e.g., of 400-600° C., all while the wafer is under an inert, e.g., nitrogen, atmosphere. The wafer is then subjected to initial oxidation, e.g., in dry oxygen, at the low oxidizing temperature to form a uniform initial thickness oxide, e.g., silicon dioxide, layer, e.g., of up to 10 angstroms, on the surface, after which the furnace temperature is increased to a high oxidizing temperature, e.g., of 700-1200° C., while the wafer is under an inert atmosphere. The wafer is next subjected to final oxidation, e.g., in oxygen and/or water vapor, at the high oxidizing temperature to increase uniformly the oxide layer to a selective final thickness, e.g., of 20-100 angstroms, whereupon the resultant uniform final thickness oxide layer-containing wafer is recovered from the furnace.
摘要翻译：提供了两步逐步热氧化工艺以改善半导体晶片制造中薄氧化物层的厚度均匀性。诸如硅的半导体晶片，具有在其上形成氧化物层但基本上不含氧化物层的表面，例如在室温下被加载到维持在低负载温度的氧化炉中，例如，400-600℃，并且将晶片温度调节至低氧化温度，例如400-600℃，同时晶片处于惰性，例如氮气氛下。然后将晶片在低氧化温度下进行初始氧化，例如在干燥的氧气中，以在表面上形成均匀的初始厚度氧化物，例如二氧化硅，例如至多10埃的层，之后炉温升高到高的氧化温度，例如700-1200℃，同时晶片处于惰性气氛。接着在高氧化温度下将晶片进行最终氧化，例如在氧气和/或水蒸气中，以将氧化物层均匀地增加至选择性最终厚度，例如20-100埃，由此得到均匀的最终厚度从炉中回收含氧化物层的晶片。

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