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1. 发明授权

US07867837B2 Process for manufacturing rounded polysilicon electrodes on semiconductor components 有权
标题翻译：在半导体元件上制造圆形多晶硅电极的工艺
公开(公告)号：US07867837B2
公开(公告)日：2011-01-11
申请号：US11795933
申请日：2006-01-13
申请人： Franz Bermann , Günther Koppitsch , Sven Schroeter
发明人： Franz Bermann , Günther Koppitsch , Sven Schroeter
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28273
摘要： A polysilicon layer provided for a polysilicon electrode (8) is patterned by means of a resist mask (5) and an auxiliary layer (4) made of a material that is suitable as an antireflection layer, the auxiliary layer (4) being provided with lateral hollowed-out recesses in such a way that the polysilicon electrode is formed with rounded edges (7) during etching. The auxiliary layer is preferably produced from a soluble material and with a thickness of 70 nm to 80 nm. A base layer (2) may be provided as a gate dielectric of memory cell transistors and additionally as an etching stop layer.
摘要翻译：设置用于多晶硅电极（8）的多晶硅层通过抗蚀剂掩模（5）和由适合作为抗反射层的材料制成的辅助层（4）构图，辅助层（4）设置有横向挖空凹槽，使得多晶硅电极在蚀刻期间形成有圆形边缘（7）。辅助层优选由可溶性材料制成，厚度为70nm至80nm。可以提供基极层（2）作为存储单元晶体管的栅极电介质，另外还可以设置为蚀刻停止层。

2. 发明申请

US20130221539A1 METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT WITH A THROUGH-CONTACT AND SEMICONDUCTOR COMPONENT WITH THROUGH-CONTACT 有权
标题翻译：通过接触和半导体元件生产具有通过接触的半导体元件的方法
公开(公告)号：US20130221539A1
公开(公告)日：2013-08-29
申请号：US13820998
申请日：2011-08-09
申请人： Jochen Kraft , Stefan Jessenig , Günther Koppitsch , Franz Schrank , Jordi Teva , Bernhard Löffler , Jörg Siegert
发明人： Jochen Kraft , Stefan Jessenig , Günther Koppitsch , Franz Schrank , Jordi Teva , Bernhard Löffler , Jörg Siegert
IPC分类号： H01L23/48 , H01L21/48
CPC分类号： H01L23/481 , H01L21/486 , H01L21/743 , H01L21/76898 , H01L2924/0002 , H01L2924/00
摘要： Through the intermetal dielectric (2) and the semiconductor material of the substrate (1) a contact hole is formed, and a contact area of a connection metal plane (3) that faces the substrate is exposed in the contact hole. A metallization (11) is applied, which forms a connection contact (12) on the contact area, a through-contact (13) in the contact hole and a connection contact (20) on a contact area facing away from the substrate and/or on a vertical conductive connection (15) of the upper metal plane (24).
摘要翻译：通过金属间电介质（2）和基板（1）的半导体材料，形成接触孔，并且在接触孔中露出面向基板的连接金属平面（3）的接触面积。施加金属化（11），其在接触区域上形成连接触点（12），接触孔中的通孔（13）和接触区域上的连接触点（20）或在上金属平面（24）的垂直导电连接（15）上。

3. 发明授权

US09443759B2 Method for producing a semiconductor device comprising a conductor layer in the semiconductor body and semiconductor body 有权
标题翻译：用于制造半导体器件的方法，该半导体器件包括半导体本体和半导体本体中的导体层
公开(公告)号：US09443759B2
公开(公告)日：2016-09-13
申请号：US14124666
申请日：2012-05-16
申请人： Rainer Minixhofer , Ewald Stückler , Martin Schrems , Günther Koppitsch , Jochen Kraft , Jordi Teva
发明人： Rainer Minixhofer , Ewald Stückler , Martin Schrems , Günther Koppitsch , Jochen Kraft , Jordi Teva
IPC分类号： H01L21/76 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76877 , H01L21/76802 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A cutout (11), which penetrates the semiconductor body, is present in the semiconductor body (1). A conductor layer (6), which is electrically conductively connected to a metal plane (3) on or over the semiconductor body, screens the semiconductor body electrically from the cutout. The conductor layer can be metal, optionally with a barrier layer (6a), or a doped region of the semiconductor body.
摘要翻译：在半导体本体（1）中存在穿过半导体本体的切口（11）。与半导体主体上或上方的金属平面（3）导电连接的导体层（6）从半导体电路屏蔽半导体本体。导体层可以是金属，任选地具有阻挡层（6a）或半导体本体的掺杂区域。

4. 发明申请

US20140191413A1 METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE COMPRISING A CONDUCTOR LAYER IN THE SEMICONDUCTOR BODY AND SEMICONDUCTOR BODY 有权
标题翻译：用于生产在半导体体和半导体体中包含导体层的半导体器件的方法
公开(公告)号：US20140191413A1
公开(公告)日：2014-07-10
申请号：US14124666
申请日：2012-05-16
申请人： Rainer Minixhofer , Ewald Stückler , Martin Schrems , Günther Koppitsch , Jochen Kraft , Jordi Teva
发明人： Rainer Minixhofer , Ewald Stückler , Martin Schrems , Günther Koppitsch , Jochen Kraft , Jordi Teva
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76877 , H01L21/76802 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A cutout (11), which penetrates the semiconductor body, is present in the semiconductor body (1). A conductor layer (6), which is electrically conductively connected to a metal plane (3) on or over the semiconductor body, screens the semiconductor body electrically from the cutout. The conductor layer can be metal, optionally with a barrier layer (6a), or a doped region of the semiconductor body.
摘要翻译：在半导体本体（1）中存在穿过半导体本体的切口（11）。与半导体主体上或上方的金属平面（3）导电连接的导体层（6）从半导体电路屏蔽半导体本体。导体层可以是金属，任选地具有阻挡层（6a）或半导体本体的掺杂区域。

5. 发明授权

US08658534B2 Method for producing a semiconductor component, and semiconductor component 有权
标题翻译：半导体元件的制造方法以及半导体元件
公开(公告)号：US08658534B2
公开(公告)日：2014-02-25
申请号：US13054614
申请日：2009-06-25
申请人： Franz Schrank , Günther Koppitsch , Michael Beutl , Sara Carniello , Jochen Kraft
发明人： Franz Schrank , Günther Koppitsch , Michael Beutl , Sara Carniello , Jochen Kraft
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L21/743 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： In an insulation layer of an SOI substrate, a connection pad is arranged. A contact hole opening above the connection pad is provided on side walls and on the connection pad with a metallization that is contacted on top side with a top metal.
摘要翻译：在SOI衬底的绝缘层中，布置有连接衬垫。在连接垫上方的接触孔开口设置在侧壁和连接垫上，金属化层与顶部金属在顶侧接触。

6. 发明申请

US20110260284A1 Method for Producing a Semiconductor Component, and Semiconductor Component 有权
标题翻译：半导体元件的制造方法以及半导体元件
公开(公告)号：US20110260284A1
公开(公告)日：2011-10-27
申请号：US13054614
申请日：2009-06-25
申请人： Franz Schrank , Günther Koppitsch , Michael Beutl , Sara Carniello , Jochen Kraft
发明人： Franz Schrank , Günther Koppitsch , Michael Beutl , Sara Carniello , Jochen Kraft
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/76898 , H01L21/743 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： In the insulation layer (2) of an SOI substrate (1), a connection pad (7) is arranged. A contact hole opening (9) above the connection pad is provided on side walls and on the connection pad with a metallization (11) that is contacted on the top side with a top metal (12).
摘要翻译：在SOI衬底（1）的绝缘层（2）中，布置有连接焊盘（7）。在连接垫上方的接触孔开口（9）设置在侧壁上和连接垫上，金属化层（11）在顶侧与顶部金属（12）接触。

7. 发明授权

US08884442B2 Method for producing a semiconductor component with a through-contact and semiconductor component with through-contact 有权
标题翻译：一种具有贯通接触的半导体部件的制造方法以及具有贯通接点的半导体部件
公开(公告)号：US08884442B2
公开(公告)日：2014-11-11
申请号：US13820998
申请日：2011-08-09
申请人： Jochen Kraft , Stefan Jessenig , Günther Koppitsch , Franz Schrank , Jordi Teva , Bernhard Löffler , Jörg Siegert
发明人： Jochen Kraft , Stefan Jessenig , Günther Koppitsch , Franz Schrank , Jordi Teva , Bernhard Löffler , Jörg Siegert
IPC分类号： H01L21/48 , H01L23/48 , H01L21/768 , H01L21/74
CPC分类号： H01L23/481 , H01L21/486 , H01L21/743 , H01L21/76898 , H01L2924/0002 , H01L2924/00
摘要： Through the intermetal dielectric (2) and the semiconductor material of the substrate (1) a contact hole is formed, and a contact area of a connection metal plane (3) that faces the substrate is exposed in the contact hole. A metallization (11) is applied, which forms a connection contact (12) on the contact area, a through-contact (13) in the contact hole and a connection contact (20) on a contact area facing away from the substrate and/or on a vertical conductive connection (15) of the upper metal plane (24).
摘要翻译：通过金属间电介质（2）和基板（1）的半导体材料，形成接触孔，并且在接触孔中露出面向基板的连接金属平面（3）的接触面积。施加金属化（11），其在接触区域上形成连接触点（12），接触孔中的通孔（13）和接触区域上的连接触头（20）或在上金属平面（24）的垂直导电连接（15）上。

8. 发明申请

US20090197407A1 Process for Manufacturing Rounded Polysilicon Electrodes on Semiconductor Components 有权
标题翻译：半导体元件制造圆形多晶硅电极的工艺
公开(公告)号：US20090197407A1
公开(公告)日：2009-08-06
申请号：US11795933
申请日：2006-01-13
申请人： Franz Bermann , Günther Koppitsch , Sven Schroeter
发明人： Franz Bermann , Günther Koppitsch , Sven Schroeter
IPC分类号： H01L21/283
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28273
摘要： A polysilicon layer provided for a polysilicon electrode (8) is patterned by means of a resist mask (5) and an auxiliary layer (4) made of a material that is suitable as an antireflection layer, the auxiliary layer (4) being provided with lateral hollowed-out recesses in such a way that the polysilicon electrode is formed with rounded edges (7) during etching. The auxiliary layer is preferably produced from a soluble material and with a thickness of 70 nm to 80 nm. A base layer (2) may be provided as a gate dielectric of memory cell transistors and additionally as an etching stop layer.
摘要翻译：设置用于多晶硅电极（8）的多晶硅层通过抗蚀剂掩模（5）和由适合作为抗反射层的材料制成的辅助层（4）构图，辅助层（4）设置有横向挖空凹槽，使得多晶硅电极在蚀刻期间形成有圆形边缘（7）。辅助层优选由可溶性材料制成，厚度为70nm至80nm。可以提供基极层（2）作为存储单元晶体管的栅极电介质，另外还可以设置为蚀刻停止层。

9. 发明授权

US07230311B2 Silicon substrate having an insulating layer 有权
标题翻译：具有绝缘层的硅衬底
公开(公告)号：US07230311B2
公开(公告)日：2007-06-12
申请号：US10498206
申请日：2002-11-27
申请人： Ewald Stückler , Günther Koppitsch
发明人： Ewald Stückler , Günther Koppitsch
IPC分类号： H01L29/00
CPC分类号： H01L21/76202 , H01L21/76224 , H01L27/08 , H01L27/1207 , H01L27/13
摘要： A silicon substrate includes plural partial areas defined on the silicon substrate such that adjacent partial areas are orientated in different directions. The plural partial areas define an insulating layer that extends from a surface of the silicon subtrate into the silicon substrate. Each of the plural partial areas includes first regions that contain silicon dioxide formed by oxidation of silicon in the silicon substrate, and second regions that contain silicon dioxide deposited onto the silicon substrate. The first regions and the second regions are oriented in a substantially same direction and are arranged side-by-side and alternately such that two first regions do not border and two second regions do not border.
摘要翻译：硅衬底包括限定在硅衬底上的多个部分区域，使得相邻的部分区域在不同方向上取向。多个部分区域限定从硅片的表面延伸到硅衬底中的绝缘层。多个部分区域中的每一个包括含有通过硅衬底中的硅的氧化形成的二氧化硅的第一区域和包含沉积在硅衬底上的二氧化硅的第二区域。第一区域和第二区域在大致相同的方向上取向并且并排布置，使得两个第一区域不会边界并且两个第二区域不相邻。

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