专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US06291296B1 Method for removing anti-reflective coating layer using plasma etch process before contact CMP 有权
标题翻译：在接触CMP之前使用等离子体蚀刻工艺去除抗反射涂层的方法
公开(公告)号：US06291296B1
公开(公告)日：2001-09-18
申请号：US09416382
申请日：1999-10-12
申请人： Angela T. Hui , Wenge Yang , Kashmir Sahota , Mark T. Ramsbey , Suzette K. Pangrle , Minh Van Ngo
发明人： Angela T. Hui , Wenge Yang , Kashmir Sahota , Mark T. Ramsbey , Suzette K. Pangrle , Minh Van Ngo
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/951
摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of an dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH3F)/oxygen (O2) etch chemistry is used to selectively remove the ARC layer without scratching and/or degradation of the dielectric layer, source/drain regions formed over the substrate, and a silicide layer formed atop stacked gate structures. The CH3F/O2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer, the source/drain regions and the silicide layer. In addition, by removing the ARC layer prior to the formation of tungsten contacts by filling of contact openings formed in the dielectric layer with tungsten, potential scratching of tungsten contacts due to ARC layer removal is eliminated.
摘要翻译：本发明提供了一种从基板表面上的电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨触点。在一个实施方案中，使用氟甲烷（CH 3 F）/氧（O 2）蚀刻化学物质来选择性地除去ARC层，而不会在电介质层，形成在衬底上的源极/漏极区域的划伤和/或降解，以及形成在顶部的硅化物层堆叠门结构。 CH3F / O2蚀刻化学以比介电层，源/漏区和硅化物层的蚀刻速率明显更快的速率蚀刻ARC层。此外，通过在形成钨触点之前，通过用钨填充形成在电介质层中的接触开口来去除ARC层，消除了由于ARC层去除引起的钨触点的潜在划痕。

12. 发明授权

US08384146B2 Methods for forming a memory cell having a top oxide spacer 有权
标题翻译：形成具有顶部氧化物间隔物的存储单元的方法
公开(公告)号：US08384146B2
公开(公告)日：2013-02-26
申请号：US13428848
申请日：2012-03-23
申请人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
发明人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/792
摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.
摘要翻译：公开了制造具有间隔层的半导体存储单元的方法。一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

13. 发明申请

US20060223278A1 Non-critical complementary masking method for poly-1 definition in flash memory device fabrication 有权
标题翻译：闪存器件制造中poly-1定义的非关键互补掩模方法
公开(公告)号：US20060223278A1
公开(公告)日：2006-10-05
申请号：US11099339
申请日：2005-04-04
申请人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun , Krishnashree Achuthan , Christopher Raeder , Christopher Foster , Harpreet Sachar , Kashmir Sahota
发明人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun , Krishnashree Achuthan , Christopher Raeder , Christopher Foster , Harpreet Sachar , Kashmir Sahota
IPC分类号： H01L21/76
CPC分类号： H01L27/105 , H01L21/3212 , H01L21/32139 , H01L21/76229 , H01L27/1052 , H01L27/11526 , H01L27/11543 , H01L27/11568
摘要： A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.
摘要翻译：公开了一种用于在半导体晶片中定义多晶硅层的方法。使用非临界掩模在聚-1沉积之前将外围的场氧化物凹入等于最终聚-1厚度的量。使用互补的非关键掩模来允许芯的CMP将浅层隔离沟的核心氧化物台面的顶部暴露出来。

14. 发明授权

US06518185B1 Integration scheme for non-feature-size dependent cu-alloy introduction 有权
标题翻译：非特征尺寸依赖的Cu合金介绍的集成方案
公开(公告)号：US06518185B1
公开(公告)日：2003-02-11
申请号：US10127521
申请日：2002-04-22
申请人： Pin-Chin Connie Wang , Fei Wang , Kashmir Sahota , Steven Avanzino , Amit Marathe , Matthew Buynoski , Ercan Adem , Christy Woo
发明人： Pin-Chin Connie Wang , Fei Wang , Kashmir Sahota , Steven Avanzino , Amit Marathe , Matthew Buynoski , Ercan Adem , Christy Woo
IPC分类号： H01L2144
CPC分类号： H01L21/76877
摘要： In the present method of fabricating a semiconductor device, openings of different configurations (for example, different aspect ratios) are provided in a dielectric layer. Substantially undoped copper is deposited over the dielectric layer, filling the openings and extending above the dielectric layer, the different configurations of the openings providing an upper surface of the substantially undoped copper that is generally non-planar. A portion of the substantially undoped copper is removed to provide a substantially planar upper surface thereof, and a layer of doped copper is deposited on the upper surface of the substantially undoped copper. An anneal step is undertaken to difffuse the doping element into the copper in the openings.
摘要翻译：在本发明的半导体装置的制造方法中，在介质层中设置不同结构（例如不同的纵横比）的开口。基本上未掺杂的铜沉积在电介质层上，填充开口并在电介质层上方延伸，开口的不同构型提供通常为非平面的基本未掺杂的铜的上表面。去除基本上未掺杂的铜的一部分以提供其基本平坦的上表面，并且在基本未掺杂的铜的上表面上沉积掺杂的铜层。进行退火步骤以将掺杂元素扩散到开口中的铜中。

15. 发明授权

US06380067B1 Method for creating partially UV transparent anti-reflective coating for semiconductors 有权
标题翻译：半导体部分UV透明抗反射涂层的制造方法
公开(公告)号：US06380067B1
公开(公告)日：2002-04-30
申请号：US09588119
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Suzette K. Pangrle , Kashmir Sahota , Christopher F. Lyons
发明人： Ramkumar Subramanian , Minh Van Ngo , Suzette K. Pangrle , Kashmir Sahota , Christopher F. Lyons
IPC分类号： H01L21302
CPC分类号： H01L21/76895 , H01L21/0276 , H01L21/76802 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： The present invention provides a method for manufacturing a semiconductor device with a bottom anti-reflective coating (BARC) that acts as an etch stop layer and does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. Contacts are then formed for each electrical device and a partially UV transparent BARC is then deposited. An inter-layer dielectric (ILD) layer is then formed and then covered with photoresist. A top ARC (TARC) is then added and the photoresist is then photolithographically processed and subsequently developed. The TARC, ILD, and BARC layers are then selectively etched down to the device contacts forming local interconnects. The photoresist and TARC are later removed, but the BARC does not require removal due to its optical transparency.
摘要翻译：本发明提供一种用于制造半导体器件的方法，该半导体器件具有用作蚀刻停止层并且不需要去除的底部抗反射涂层（BARC）。在一个实施例中，电子器件形成在半导体衬底上。然后为每个电气设备形成触点，然后沉积部分UV透明的BARC。然后形成层间电介质（ILD）层，然后用光致抗蚀剂覆盖。然后加入顶部ARC（TARC），然后对光致抗蚀剂进行光刻处理并随后显影。然后将TARC，ILD和BARC层选择性地刻蚀成形成局部互连的器件触点。光致抗蚀剂和TARC随后被去除，但由于其光学透明性，BARC不需要去除。

16. 发明授权

US06359307B1 Method for forming self-aligned contacts and interconnection lines using dual damascene techniques 有权
标题翻译：使用双镶嵌技术形成自对准触点和互连线的方法
公开(公告)号：US06359307B1
公开(公告)日：2002-03-19
申请号：US09493436
申请日：2000-01-29
申请人： Fei Wang , Hiroyuki Kinoshita , Kashmir Sahota , Yu Sun , Wenge Yang
发明人： Fei Wang , Hiroyuki Kinoshita , Kashmir Sahota , Yu Sun , Wenge Yang
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L23/485 , H01L27/115 , H01L27/11521 , H01L2924/0002 , H01L2924/3011 , Y02P80/30 , H01L2924/00
摘要： The present invention further provides a method for forming self-aligned contacts using a dual damascene techniques that reduces the number of process steps and results in a reduction in cycle time, cost and yield loss. In a preferred embodiment, a method for forming a contact and a channel in a dielectric layer over a region on a semiconductor substrate is provided. The contact is self-aligned. The contact and channel are formed by (1) forming a contact opening in the dielectric layer, (2) forming a channel opening in the dielectric layer, wherein the channel opening encompasses the contact opening, (3) extending the contact opening to expose a portion of the region on the semiconductor substrate; and (4) filling the contact opening and the channel opening with a conductive material to form a contact and a channel, respectively.
摘要翻译：本发明还提供了一种使用双镶嵌技术形成自对准接触的方法，其减少了工艺步骤的数量并导致了循环时间，成本和屈服损失的降低。在优选实施例中，提供了在半导体衬底上的区域上形成电介质层中的接触和沟道的方法。联系人自行对齐。接触和通道由（1）在电介质层中形成接触开口形成，（2）在电介质层中形成通道开口，其中通道开口包围接触开口，（3）延伸接触开口以露出所述半导体衬底上的所述区域的部分; 和（4）分别用导电材料填充接触开口和通道开口以形成接触和通道。

17. 发明授权

US06294460B1 Semiconductor manufacturing method using a high extinction coefficient dielectric photomask 有权
标题翻译：使用高消光系数电介质光掩模的半导体制造方法
公开(公告)号：US06294460B1
公开(公告)日：2001-09-25
申请号：US09586254
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Suzette K. Pangrle , Kashmir Sahota
发明人： Ramkumar Subramanian , Minh Van Ngo , Suzette K. Pangrle , Kashmir Sahota
IPC分类号： H01L214763
CPC分类号： H01L21/7688 , H01L21/76802 , Y10S438/952
摘要： A method is provided for manufacturing a semiconductor with fewer steps and minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in conjunction with a thin photoresist layer. In one embodiment, an etch-stop layer is deposited on a semiconductor substrate, a dielectric layer is deposited on top of the etch-stop layer, and a BARC is deposited on top of the dielectric layer. The BARC is deposited by PECVD to enrich the BARC with semiconductor material to increase the extinction coefficient of the BARC so its thickness can be reduced. A photoresist layer with a thickness less than the thickness of the BARC is then deposited on top of the BARC. The photoresist is then patterned, photolithographically processed, developed, and removed. The BARC is then etched away in the pattern developed on the photoresist and the photoresist is then removed. The BARC is then used as a mask for the etching of the dielectric layer. A conductive material is deposited over the BARC and the dielectric layer and is subsequently removed in the process of polishing the conductive material without requiring a separate BARC removal step.
摘要翻译：提供了一种通过使用SiON作为底部抗反射（BARC）层和与薄的光致抗蚀剂层结合的硬掩模来制造具有较少步骤和最小化蚀刻工艺的半导体的方法。在一个实施例中，蚀刻停止层沉积在半导体衬底上，电介质层沉积在蚀刻停止层的顶部，并且BARC沉积在电介质层的顶部上。 BARC通过PECVD沉积，以使BARC富集半导体材料，以增加BARC的消光系数，从而减小其厚度。然后将厚度小于BARC的厚度的光致抗蚀剂层沉积在BARC的顶部。然后将光致抗蚀剂图案化，光刻加工，显影和除去。然后将BARC以在光致抗蚀剂上显影的图案蚀刻掉，然后除去光致抗蚀剂。然后将BARC用作蚀刻电介质层的掩模。导电材料沉积在BARC和电介质层上，随后在抛光导电材料的过程中被去除，而不需要单独的BARC去除步骤。

18. 发明授权

US6124640A Scalable and reliable integrated circuit inter-level dielectric 有权
标题翻译：可扩展和可靠的集成电路级间电介质
公开(公告)号：US6124640A
公开(公告)日：2000-09-26
申请号：US144506
申请日：1998-08-31
申请人： Kashmir Sahota , Richard J. Huang , Hung-Sheng Chen , Yu Sun
发明人： Kashmir Sahota , Richard J. Huang , Hung-Sheng Chen , Yu Sun
IPC分类号： H01L21/3105 , H01L21/314 , H01L21/316 , H01L21/768 , H01L51/00
CPC分类号： H01L21/76837 , H01L21/76834 , H01L21/31051 , H01L21/3145 , H01L21/31612
摘要： An inter-level dielectric (ILD) is formed from a lower barrier layer comprising a conformal silicon oxynitride layer, a gap fill layer comprising a high-density plasma (HDP) oxide and a cap layer. The use of HDP oxide as a gap fill layer enables better control of the ILD thickness, avoids outgasing problems, facilitates via formation and reduces planarization.
摘要翻译：层间电介质（ILD）由包括保形氮氧化硅层的下阻挡层，包含高密度等离子体（HDP）氧化物和盖层的间隙填充层形成。使用HDP氧化物作为间隙填充层能够更好地控制ILD厚度，避免出现问题，便于通孔形成并减少平坦化。

19. 发明授权

US5998301A Method and system for providing tapered shallow trench isolation structure profile 失效
标题翻译：提供锥形浅沟槽隔离结构轮廓的方法和系统
公开(公告)号：US5998301A
公开(公告)日：1999-12-07
申请号：US993252
申请日：1997-12-18
申请人： Tuan D. Pham , Angela T. Hui , Kashmir Sahota
发明人： Tuan D. Pham , Angela T. Hui , Kashmir Sahota
IPC分类号： H01L21/8247 , H01L21/76 , H01L21/762 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/308
CPC分类号： H01L21/76232 , H01L21/76237
摘要： A method and system for providing a shallow trench isolation structure profile on a semiconductor is disclosed. The method and system includes patterning a mask on the semiconductor substrate, etching the mask such that the mask has sloped sides, etching the semiconductor substrate to form a trench whereby the trench has tapered sides, and planarizing the semiconductor substrate to optimize the trench depth and the width of the trench opening for subsequent processes. According to the method and system disclosed herein, the present invention allows a shallow trench isolation structure profile to be formed which has tapered sides.
摘要翻译：公开了一种用于在半导体上提供浅沟槽隔离结构轮廓的方法和系统。该方法和系统包括在半导体衬底上图案化掩模，蚀刻掩模使得掩模具有倾斜的侧面，蚀刻半导体衬底以形成沟槽，由此沟槽具有锥形侧面，并平坦化半导体衬底以优化沟槽深度，用于后续处理的沟槽开口的宽度。根据本文公开的方法和系统，本发明允许形成具有锥形侧面的浅沟槽隔离结构轮廓。

20. 发明申请

US20120181601A1 METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER 有权
标题翻译：用于形成具有顶部氧化物间隔物的存储单元的方法
公开(公告)号：US20120181601A1
公开(公告)日：2012-07-19
申请号：US13428848
申请日：2012-03-23
申请人： Shenqing FANG , Angela HUI , Gang XUE , Alexander NICKEL , Kashmir SAHOTA , Scott BELL , Chun CHEN , Wai LO
发明人： Shenqing FANG , Angela HUI , Gang XUE , Alexander NICKEL , Kashmir SAHOTA , Scott BELL , Chun CHEN , Wai LO
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/792
摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.
摘要翻译：公开了制造具有间隔层的半导体存储单元的方法。一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式