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11. 发明授权

US09003160B2 Active buffered memory 有权
标题翻译：主动缓冲内存
公开(公告)号：US09003160B2
公开(公告)日：2015-04-07
申请号：US13566019
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
IPC分类号： G06F12/10 , G06F9/445
CPC分类号： G06F9/44578 , G06F12/10 , Y02D10/13
摘要： According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address.
摘要翻译：根据本发明的一个实施例，一种用于操作包括存储器和处理元件的存储器件的方法包括在处理元件中接收来自请求器的命令，在处理元件中接收基于该命令的程序所述程序包括从所述存储器中的第一存储器位置加载的加载指令，并且由所述处理元件执行所述程序，所述执行包括来自所述存储器中的第二存储器位置的所述处理元件中的加载数据。该方法还包括由处理元件基于加载指令产生第二存储器位置的虚拟地址，并由处理元件将虚拟地址转换为实际地址。

12. 发明申请

US20140040592A1 ACTIVE BUFFERED MEMORY 有权
标题翻译：主动缓冲存储器
公开(公告)号：US20140040592A1
公开(公告)日：2014-02-06
申请号：US13566019
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
IPC分类号： G06F12/10
CPC分类号： G06F9/44578 , G06F12/10 , Y02D10/13
摘要： According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address.
摘要翻译：根据本发明的一个实施例，一种用于操作包括存储器和处理元件的存储器件的方法包括在处理元件中接收来自请求器的命令，在处理元件中接收基于该命令的程序所述程序包括从所述存储器中的第一存储器位置加载的加载指令，并且由所述处理元件执行所述程序，所述执行包括来自所述存储器中的第二存储器位置的所述处理元件中的加载数据。该方法还包括由处理元件基于加载指令产生第二存储器位置的虚拟地址，并由处理元件将虚拟地址转换为实际地址。

13. 发明申请

US20120284720A1 HARDWARE ASSISTED SCHEDULING IN COMPUTER SYSTEM 审中-公开
标题翻译：计算机系统中的硬件辅助调度
公开(公告)号：US20120284720A1
公开(公告)日：2012-11-08
申请号：US13102389
申请日：2011-05-06
申请人： Harold W. Cain, III , Hubertus Franke , Charles R. Johns , James A. Kahle , Hung Q. Le , Ravi Nair
发明人： Harold W. Cain, III , Hubertus Franke , Charles R. Johns , James A. Kahle , Hung Q. Le , Ravi Nair
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/5018
摘要： Apparatus and methods for hardware assisted scheduling of software tasks in a computer system are disclosed. For example, a computer system comprises a first pool for maintaining a set of executable software threads, a first scheduler, a second pool for maintaining a set of active software threads, and a second scheduler. The first scheduler assigns a subset of the set of executable software threads to the set of active software threads and the second scheduler dispatches one or more threads from the set of active software threads to a set of hardware threads for execution. In one embodiment, the first scheduler is implemented as part of the operating system of the computer system, and the second scheduler is implemented in hardware.
摘要翻译：公开了一种用于计算机系统中的软件任务的硬件辅助调度的装置和方法。例如，计算机系统包括用于维护一组可执行软件线程的第一池，第一调度器，用于维护一组活动软件线程的第二池和第二调度器。第一调度器将该组可执行软件线程的子集分配给该组活动软件线程，并且第二调度器将一个或多个线程从该组活动软件线程调度到一组用于执行的硬件线程。在一个实施例中，第一调度器被实现为计算机系统的操作系统的一部分，并且第二调度器以硬件实现。

14. 发明申请

US20120005473A1 Secure Dynamically Reconfigurable Logic 有权
标题翻译：安全动态可重构逻辑
公开(公告)号：US20120005473A1
公开(公告)日：2012-01-05
申请号：US12827726
申请日：2010-06-30
申请人： H. Peter Hofstee , James A. Kahle , Michael A. Paolini
发明人： H. Peter Hofstee , James A. Kahle , Michael A. Paolini
IPC分类号： G06F1/24
CPC分类号： G06F21/76 , G06F15/7867
摘要： A mechanism for securely and dynamically reconfiguring reconfigurable logic is provided. A state machine within a data processing system establishes a hardware boundary to the reconfigurable logic within the data processing system thereby forming isolated reconfigurable logic. The state machine clears any prior state existing within the isolated reconfigurable logic. The state machine authenticates a new configuration to be loaded into the isolated reconfigurable logic. The state machine determines whether the authentication of the new configuration is successful. Responsive to the authentication of the new configuration being successful, the state machine loads the new configuration into the isolated reconfigurable logic. The state machine then starts operation of the isolated reconfigurable logic.
摘要翻译：提供了一种用于安全和动态地重新配置可重构逻辑的机制。数据处理系统内的状态机为数据处理系统内的可重构逻辑建立硬件边界，从而形成隔离的可重配置逻辑。状态机清除分离的可重新配置逻辑中存在的任何先前状态。状态机验证要加载到隔离可重配置逻辑中的新配置。状态机确定新配置的认证是否成功。响应于新配置的认证成功，状态机将新配置加载到隔离的可重配置逻辑中。状态机然后启动隔离的可重新配置逻辑的操作。

15. 发明授权

US5802386A Latency-based scheduling of instructions in a superscalar processor 失效
标题翻译：超标量处理器中的指令的基于延迟的调度
公开(公告)号：US5802386A
公开(公告)日：1998-09-01
申请号：US751347
申请日：1996-11-19
申请人： James A. Kahle , Soummya Mallick , Robert G. McDonald
发明人： James A. Kahle , Soummya Mallick , Robert G. McDonald
IPC分类号： G06F9/38 , G06F9/34
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855
摘要： Instructions are efficiently scheduled for execution based on a stored identification of the first processor cycle when a result of a previous instruction required as an operand for the instruction to be scheduled will become available. Examination of stored processor cycle identifications for the operands of an instruction reveals the earliest processor cycle when the instruction may be executed. By selecting the greater of the largest stored processor cycle identification for an operand of the instruction and the earliest available processor cycle for an execution unit required to execute the instruction, the instruction is efficiently scheduled for the earliest possible execution. Latency of previous instructions in generating an operand of the instruction being scheduled is automatically accommodated.
摘要翻译：当作为要调度的指令的操作数需要的先前指令的结果将变得可用时，基于存储的第一处理器周期的标识，有效地调度执行指令。对指令的操作数的存储处理器周期标识的检查显示指令执行时的最早处理器周期。通过选择指令操作数的最大的存储处理器周期标识中较大的一个，以及执行指令所需的执行单元的最早的可用处理器周期，该指令被有效地调度以进行最早的执行。自动容纳用于生成正在调度的指令的操作数的先前指令的延迟。

16. 发明授权

US5539681A Circuitry and method for reducing power consumption within an electronic circuit 失效
公开(公告)号：US5539681A
公开(公告)日：1996-07-23
申请号：US583204
申请日：1996-01-04
申请人： Michael C. Alexander , Arturo L. Arizpe , Gianfranco Gerosa , James A. Kahle , Aubrey D. Ogden
发明人： Michael C. Alexander , Arturo L. Arizpe , Gianfranco Gerosa , James A. Kahle , Aubrey D. Ogden
IPC分类号： G06F1/04 , G06F1/32 , G06F9/30 , G06F9/38 , G06F15/78
CPC分类号： G06F9/3885 , G06F1/3203 , G06F1/324 , Y02B60/1217
摘要： A method and circuitry are provided, in which a first operation is performed with first circuitry. A second operation is performed with second circuitry. A first signal is generated in response to the first operation. A second signal is generated in response to the second operation. Power consumption is adjusted within the second circuitry in response to the first and second signals.

17. 发明授权

US5467473A Out of order instruction load and store comparison 失效
标题翻译：无序指令加载和存储比较
公开(公告)号：US5467473A
公开(公告)日：1995-11-14
申请号：US1976
申请日：1993-01-08
申请人： James A. Kahle , Chin-Cheng Kau
发明人： James A. Kahle , Chin-Cheng Kau
IPC分类号： G06F9/38
CPC分类号： G06F9/3834
摘要： A processing system allows for out of order instruction execution and includes at least one load/store unit for loading instructions to a register for processing by a fixed point unit, floating point unit, or the like, and store the results to memory. A load queue maintains the addresses and program numbers of the load instructions. During execution the address of the store instruction is compared to the address in the load queue of previously executed load instructions. A program counter compares the program number of the store instruction with the program number of the load instruction in the load queue. If the addresses are different, then no impermissible out of order situation exists between the load and store instructions being compared, because the data is not at the same address. If the address is the same, and the store program number is greater than the load program number, then the instructions have been executed in order (the load correctly preceded the store) and no problem exists. However, if the addresses are the same and the load instruction has been incorrectly reordered to precede the store instruction, then a reordering conflict exists and the load instructions must be re-executed.
摘要翻译：处理系统允许执行不一致的指令，并且包括至少一个加载/存储单元，用于将指令加载到寄存器以由固定点单元，浮点单元等进行处理，并将结果存储到存储器中。加载队列维护加载指令的地址和程序号。在执行期间，将存储指令的地址与先前执行的加载指令的加载队列中的地址进行比较。程序计数器将存储指令的程序号与加载队列中的加载指令的程序号进行比较。如果地址不同，那么由于数据不在相同的地址，所以在被比较的加载和存储指令之间不存在无序的情况。如果地址相同，并且存储程序号大于加载程序号，则指令已按顺序执行（加载正确存储在存储之前），并且不存在问题。然而，如果地址相同并且加载指令已被错误地重新排序到存储指令之前，则存在重新排序冲突，并且必须重新执行加载指令。

18. 发明授权

US5465373A Method and system for single cycle dispatch of multiple instructions in a superscalar processor system 失效
标题翻译：用于超标量处理器系统中多个指令的单周期调度的方法和系统
公开(公告)号：US5465373A
公开(公告)日：1995-11-07
申请号：US1864
申请日：1993-01-08
申请人： James A. Kahle , Chin-Cheng Kau , David S. Levitan , Aubrey D. Ogden , Ali A. Poursepanj , Paul K.-G. Tu , Donald E. Waldecker
发明人： James A. Kahle , Chin-Cheng Kau , David S. Levitan , Aubrey D. Ogden , Ali A. Poursepanj , Paul K.-G. Tu , Donald E. Waldecker
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/384
摘要： A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.
摘要翻译：一种用于在超标量处理器系统中允许单周期指令调度的方法和系统，其将多个指令同时分配到一组执行单元以执行并将其结果放置在指定的通用寄存器内。每个指令通常包括至少一个源操作数和一个目的操作数。提供多个中间存储缓冲器，并且每当将指令分派到可用执行单元时，中间存储缓冲器中的特定一个被分配给调度指令内的任何目的地操作数，允许在单个周期内发送指令通过消除对确定和选择指定的通用寄存器或指定的备用通用寄存器的任何要求。

19. 发明授权

US5420808A Circuitry and method for reducing power consumption within an electronic circuit 失效
标题翻译：用于降低电子电路内功耗的电路和方法
公开(公告)号：US5420808A
公开(公告)日：1995-05-30
申请号：US61397
申请日：1993-05-13
申请人： Michael C. Alexander , Arturo L. Arizpe , Gianfranco Gerosa , James A. Kahle , Aubrey D. Ogden
发明人： Michael C. Alexander , Arturo L. Arizpe , Gianfranco Gerosa , James A. Kahle , Aubrey D. Ogden
IPC分类号： G06F1/04 , G06F1/32 , G06F9/30 , G06F9/38 , G06F15/78
CPC分类号： G06F9/3885 , G06F1/3203 , G06F1/324 , Y02B60/1217
摘要： A method and circuitry are provided, in which a first operation is performed with first circuitry. A second operation is performed with second circuitry. A first signal is generated in response to the first operation. A second signal is generated in response to the second operation. Power consumption is adjusted within the second circuitry in response to the first and second signals.
摘要翻译：提供了一种方法和电路，其中利用第一电路执行第一操作。用第二电路执行第二操作。响应于第一操作产生第一信号。响应于第二操作产生第二信号。响应于第一和第二信号在第二电路内调节功耗。

20. 发明授权

US5075840A Tightly coupled multiprocessor instruction synchronization 失效
标题翻译：轻巧的多协议指令同步
公开(公告)号：US5075840A
公开(公告)日：1991-12-24
申请号：US297783
申请日：1989-01-13
申请人： Gregory F. Grohoski , James A. Kahle , Myhong Nguyenphu , David S. Ray
发明人： Gregory F. Grohoski , James A. Kahle , Myhong Nguyenphu , David S. Ray
IPC分类号： G06F15/16 , G06F9/38 , G06F9/48
CPC分类号： G06F9/4812 , G06F9/3822 , G06F9/3836 , G06F9/3861 , G06F9/3877 , G06F9/3885
摘要： A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

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