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11. 发明申请

US20080081385A1 METHODS AND SYSTEMS FOR INSPECTION OF WAFERS AND RETICLES USING DESIGNER INTENT DATA 审中-公开
标题翻译：使用设计者信息数据检查波形和反射的方法和系统
公开(公告)号：US20080081385A1
公开(公告)日：2008-04-03
申请号：US11939983
申请日：2007-11-14
申请人： Paul Marella , Sharon McCauley , Ellis Chang , William Volk , James Wiley , Sterling Watson , Sagar Kekare , Carl Hess
发明人： Paul Marella , Sharon McCauley , Ellis Chang , William Volk , James Wiley , Sterling Watson , Sagar Kekare , Carl Hess
IPC分类号： H01L21/66
CPC分类号： G06T7/0006 , G01N21/9501 , G01N21/956 , G01N2021/95676 , G03F1/84 , G03F7/7065 , G06T7/0008 , G06T2207/30148
摘要： Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.
摘要翻译：提供了使用设计人员意图数据检查晶圆和标线的方法和系统。一种计算机实现的方法包括基于通过检查光罩产生的检查数据来识别晶片上的有害缺陷，其用于在晶片检查之前在晶片上形成图案。另一种计算机实现的方法包括通过分析通过检查晶片产生的数据来结合表示标线的数据来检测晶片上的缺陷，该数据包括标识掩模版的不同类型的部分的标记。附加的计算机实现的方法包括基于改变晶片上形成的器件的特性的缺陷来确定用于处理晶片的制造工艺的特性。进一步的计算机实现的方法包括基于通过检查晶片产生的数据来改变或模拟集成电路的设计的一个或多个特性。

12. 发明申请

US20050004774A1 Methods and systems for inspection of wafers and reticles using designer intent data 有权
标题翻译：使用设计人员意图数据检查晶圆和标线片的方法和系统
公开(公告)号：US20050004774A1
公开(公告)日：2005-01-06
申请号：US10883372
申请日：2004-07-01
申请人： William Volk , James Wiley , Sterling Watson , Sagar Kekare , Carl Hess , Paul Marella , Sharon McCauley , Ellis Chang
发明人： William Volk , James Wiley , Sterling Watson , Sagar Kekare , Carl Hess , Paul Marella , Sharon McCauley , Ellis Chang
IPC分类号： G01N21/95 , G03F1/44 , G03F7/20 , G01N21/00
CPC分类号： G06T7/0006 , G01N21/9501 , G01N21/956 , G01N2021/95676 , G03F1/84 , G03F7/7065 , G06T7/0008 , G06T2207/30148
摘要： Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.
摘要翻译：提供了使用设计人员意图数据检查晶圆和标线的方法和系统。一种计算机实现的方法包括基于通过检查光罩产生的检查数据来识别晶片上的有害缺陷，其用于在晶片检查之前在晶片上形成图案。另一种计算机实现的方法包括通过分析通过检查晶片产生的数据来结合表示标线的数据来检测晶片上的缺陷，该数据包括标识掩模版的不同类型的部分的标记。附加的计算机实现的方法包括基于改变晶片上形成的器件的特性的缺陷来确定用于处理晶片的制造工艺的特性。进一步的计算机实现的方法包括基于通过检查晶片产生的数据来改变或模拟集成电路的设计的一个或多个特性。

13. 发明授权

US09002497B2 Methods and systems for inspection of wafers and reticles using designer intent data 有权
标题翻译：使用设计人员意图数据检查晶圆和标线片的方法和系统
公开(公告)号：US09002497B2
公开(公告)日：2015-04-07
申请号：US10883372
申请日：2004-07-01
申请人： William Volk , James Wiley , Sterling Watson , Sagar A. Kekare , Carl Hess , Paul Frank Marella , Sharon McCauley , Ellis Chang
发明人： William Volk , James Wiley , Sterling Watson , Sagar A. Kekare , Carl Hess , Paul Frank Marella , Sharon McCauley , Ellis Chang
IPC分类号： G06F19/00 , G03F1/84 , G01N21/95 , G01N21/956 , G03F7/20
CPC分类号： G06T7/0006 , G01N21/9501 , G01N21/956 , G01N2021/95676 , G03F1/84 , G03F7/7065 , G06T7/0008 , G06T2207/30148
摘要： Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.
摘要翻译：提供了使用设计人员意图数据检查晶圆和标线的方法和系统。一种计算机实现的方法包括基于通过检查光罩产生的检查数据来识别晶片上的有害缺陷，其用于在晶片检查之前在晶片上形成图案。另一种计算机实现的方法包括通过分析通过检查晶片产生的数据来结合表示标线的数据来检测晶片上的缺陷，该数据包括标识掩模版的不同类型的部分的标记。附加的计算机实现的方法包括基于改变晶片上形成的器件的特性的缺陷来确定用于处理晶片的制造工艺的特性。进一步的计算机实现的方法包括基于通过检查晶片产生的数据来改变或模拟集成电路的设计的一个或多个特性。

14. 发明授权

US08559001B2 Inspection guided overlay metrology 有权
公开(公告)号：US08559001B2
公开(公告)日：2013-10-15
申请号：US12984679
申请日：2011-01-05
申请人： Ellis Chang , Amir Widmann , Allen Park
发明人： Ellis Chang , Amir Widmann , Allen Park
IPC分类号： G01N21/00 , G01R31/26
CPC分类号： G01N21/9501 , G01N21/95607 , G01N2021/8822 , G03F7/70633 , G03F7/7065 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.

15. 发明申请

US20110187848A1 COMPUTER-IMPLEMENTED METHODS, COMPUTER-READABLE MEDIA, AND SYSTEMS FOR CLASSIFYING DEFECTS DETECTED IN A MEMORY DEVICE AREA ON A WAFER 有权
标题翻译：计算机实现方法，计算机可读介质和用于分类在WAFER中的存储器设备区域中检测到的缺陷的系统
公开(公告)号：US20110187848A1
公开(公告)日：2011-08-04
申请号：US13056623
申请日：2009-07-28
申请人： SunYong Choi , YeonHo Pae , Ellis Chang
发明人： SunYong Choi , YeonHo Pae , Ellis Chang
IPC分类号： H04N7/18 , G06K9/00
CPC分类号： G11C29/56 , G11C29/56008
摘要： Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer are provided.
摘要翻译：提供了计算机实现的方法，计算机可读介质和用于分类在晶片上的存储器件区域中检测到的缺陷的系统。

16. 发明授权

US07904845B2 Determining locations on a wafer to be reviewed during defect review 有权
标题翻译：确定在缺陷审查期间待审查的晶圆上的位置
公开(公告)号：US07904845B2
公开(公告)日：2011-03-08
申请号：US11950961
申请日：2007-12-05
申请人： Christophe Fouquet , Gordon Abbott , Ellis Chang , Zain K. Saidin
发明人： Christophe Fouquet , Gordon Abbott , Ellis Chang , Zain K. Saidin
IPC分类号： G06F17/50
CPC分类号： G03F1/84 , G03F7/7065
摘要： Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects detected on the wafer. The method also includes determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.
摘要翻译：提供了各种方法，设计，缺陷评估工具和用于在缺陷评估期间确定待检查的晶片上的位置的系统。一种计算机实现的方法包括获取由两个或更多个检查系统检测到的缺陷的坐标。缺陷不包括在晶片上检测到的缺陷。该方法还包括通过将缺陷的坐标转换为晶片上的坐标来确定在缺陷审查期间待审查的晶片上的位置的坐标，使得可以使用在位置处执行的缺陷评估的结果来确定是否缺陷导致晶片上的系统缺陷。

17. 发明申请

US20160196379A1 METROLOGY TARGET INDENTIFICATION, DESIGN AND VERIFICATION 有权
标题翻译：计量目标识别，设计和验证
公开(公告)号：US20160196379A1
公开(公告)日：2016-07-07
申请号：US14356551
申请日：2014-03-04
申请人： Michael Adel , Tal Shusterman , Chen Dror , Ellis Chang
发明人： Michael Adel , Tal Shusterman , Chen Dror , Ellis Chang
IPC分类号： G06F17/50 , G03F1/36
CPC分类号： G06F17/5081 , G03F1/36 , G03F7/70625 , G03F7/70633 , G03F7/70683 , H01L22/12 , H01L22/30
摘要： A metrology design and verification framework is provided, which includes methods and systems for metrology structure identification in an integrated circuit design data block, design rule checking, hierarchal design of metrology target structures to minimize random errors, and metrology design rule verification of metrology target design files. In-die metrology targets are identified using various filtering methods and/or designed as hierarchical structure within dies or outside the dies. Particularly, metrology target design files are generated, which are hierarchical in structure and compatible with design rule checks. Design rule check takes into account the hierarchical and often repetitive target designs in the verification process. Layouts may be verified using design rule checks at different levels of design rules, which may be combined to remove rule violations and errors prior to actual target production.
摘要翻译：提供了一种计量设计和验证框架，其中包括集成电路设计数据块中的计量结构识别的方法和系统，设计规则检查，度量目标结构的层次设计以最小化随机误差，以及度量目标设计的计量设计规则验证文件。使用各种滤波方法和/或在模具内或模具外部设计为分层结构来识别模内计量目标。特别地，生成了计量目标设计文件，其结构是分级的，与设计规则检查兼容。设计规则检查在验证过程中考虑了层次结构和经常重复的目标设计。可以使用不同级别的设计规则的设计规则检查来验证布局，其可以组合以在实际目标生产之前去除规则违规和错误。

18. 发明授权

US08594823B2 Scanner performance comparison and matching using design and defect data 有权
标题翻译：使用设计和缺陷数据扫描仪性能比较和匹配
公开(公告)号：US08594823B2
公开(公告)日：2013-11-26
申请号：US12919757
申请日：2010-07-12
申请人： Allen Park , Ellis Chang , Masami Aoki , Chris Chih-Chien Young , Martin Plihal , Michael John Van Riet
发明人： Allen Park , Ellis Chang , Masami Aoki , Chris Chih-Chien Young , Martin Plihal , Michael John Van Riet
IPC分类号： G06F19/00 , H01L21/66
CPC分类号： H01L22/12 , G03F7/70516 , G03F7/70625 , G03F7/70641 , G03F7/7065
摘要： A system and method of matching multiple scanners using design and defect data are described. A golden wafer is processed using a golden tool. A second wafer is processed using a second tool. Both tools provide focus/exposure modulation. Wafer-level spatial signatures of critical structures for both wafers can be compared to evaluate the behavior of the scanners. Critical structures can be identified by binning defects on the golden wafer having similar patterns. In one embodiment, the signatures must match within a certain percentage or the second tool is characterized as a “no match”. Reticles can be compared in a similar manner, wherein the golden and second wafers are processed using a golden reticle and a second reticle, respectively.
摘要翻译：描述使用设计和缺陷数据匹配多个扫描仪的系统和方法。使用金色工具处理金色晶圆。使用第二工具处理第二晶片。两种工具都提供对焦/曝光调制。可以比较两个晶片的关键结构的晶片级空间特征，以评估扫描仪的行为。关键结构可以通过在具有相似图案的金色晶片上合并缺陷来识别。在一个实施例中，签名必须在一定百分比内匹配，或者第二工具被表征为“不匹配”。可以以类似的方式比较网状物，其中分别使用金色掩模版和第二掩模版来处理金色和第二晶片。

19. 发明申请

US20130064442A1 Determining Design Coordinates for Wafer Defects 有权
标题翻译：确定晶圆缺陷的设计坐标
公开(公告)号：US20130064442A1
公开(公告)日：2013-03-14
申请号：US13601891
申请日：2012-08-31
申请人： Ellis Chang , Michael J. Van Riet , Allen Park , Khurram Zafar , Santosh Bhattacharyya
发明人： Ellis Chang , Michael J. Van Riet , Allen Park , Khurram Zafar , Santosh Bhattacharyya
IPC分类号： G06K9/62
CPC分类号： G06T7/001 , G06T7/74 , G06T2207/30148
摘要： Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.
摘要翻译：提供了用于确定在晶片上检测到的缺陷的设计坐标的方法和系统。一种方法包括对准晶片的设计以通过检查工具对晶片上的多个条带中检测到的缺陷来检查工具图像，基于对准的结果确定每个缺陷在设计坐标中的位置，分别确定缺陷基于检测到每个缺陷的条带（条纹校正因子），每个缺陷的设计坐标以及由检查工具确定的每个缺陷的位置，针对每个多个条带的位置偏移，以及通过对这些缺陷应用适当的条纹校正因子来确定检测工具在多个条中检测到的其他缺陷的设计坐标。

20. 发明申请

US20120316855A1 Using Three-Dimensional Representations for Defect-Related Applications 审中-公开
标题翻译：使用三维表示缺陷相关应用程序
公开(公告)号：US20120316855A1
公开(公告)日：2012-12-13
申请号：US13156323
申请日：2011-06-08
申请人： Allen Park , Ellis Chang , Prashant A. Aji , Steven R. Lange
发明人： Allen Park , Ellis Chang , Prashant A. Aji , Steven R. Lange
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G01N21/9501 , G06F17/50 , G06F17/5009 , G06F2217/12 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments for using three-dimensional representations for defect-related applications are provided.
摘要翻译：提供了用于缺陷相关应用的三维表示的各种实施例。

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