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151. 发明授权

US07313780B2 System and method for designing semiconductor photomasks 有权
标题翻译：设计半导体光掩模的系统和方法
公开(公告)号：US07313780B2
公开(公告)日：2007-12-25
申请号：US11078820
申请日：2005-03-10
申请人： Andrew Khoh , Byong-Il Choi , Lap Chan , Ganesh Samudra , Yihong Wu
发明人： Andrew Khoh , Byong-Il Choi , Lap Chan , Ganesh Samudra , Yihong Wu
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A trial semiconductor photomask design having discontinuity points is provided, and each of the discontinuity points is treated as simulated light sources. Simulated light from each of the simulated light sources is focused, and a composite image intensity of the focused simulated light is calculated to verify the trial semiconductor photomask design. The trial semiconductor photomask design is sharpened. A photomask design specification is generated for use in fabricating such a photomask.
摘要翻译：提供具有不连续点的试验半导体光掩模设计，将每个不连续点视为模拟光源。聚焦每个模拟光源的模拟光，并计算聚焦模拟光的合成图像强度，以验证试验半导体光掩模设计。试制半导体光掩模设计锐化。生成光掩模设计规范用于制造这种光掩模。

152. 发明授权

US07250669B2 Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
标题翻译：通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程
公开(公告)号：US07250669B2
公开(公告)日：2007-07-31
申请号：US10909523
申请日：2004-08-02
申请人： Lap Chan , Sanford Chu , Chit Hwei Ng , Purakh Verma , Jia Zhen Zheng , Johnny Chew , Choon Beng Sia
发明人： Lap Chan , Sanford Chu , Chit Hwei Ng , Purakh Verma , Jia Zhen Zheng , Johnny Chew , Choon Beng Sia
IPC分类号： H01L29/00
CPC分类号： H01L21/764 , H01L21/26506
摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.
摘要翻译：降低半导体器件衬底效应的第一种方法包括以下步骤。选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。在所述至少一个上介电层上形成钝化层。图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

153. 发明授权

US07238971B2 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US07238971B2
公开(公告)日：2007-07-03
申请号：US11123748
申请日：2005-05-04
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L29/732
CPC分类号： H01L29/66242 , H01L29/737
摘要： A lateral heterojunction bipolar transistor (HBT) comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

154. 发明授权

US07022578B2 Heterojunction bipolar transistor using reverse emitter window 有权
标题翻译：使用反向发射极窗口的异质结双极晶体管
公开(公告)号：US07022578B2
公开(公告)日：2006-04-04
申请号：US10683713
申请日：2003-10-09
申请人： Purakh Raj Verma , Shao-fu Sanford Chu , Lap Chan , Jian Xun Li , Zhen Jia Zheng
发明人： Purakh Raj Verma , Shao-fu Sanford Chu , Lap Chan , Jian Xun Li , Zhen Jia Zheng
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/41708 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, an intrinsic base region of a compound semiconductive material over the collector region, an extrinsic base region, an emitter structure, an interlevel dielectric layer over the collector region, extrinsic base region and emitter structure, and connections through the interlevel dielectric layer to the base region, the emitter structure, and the collector region. The emitter structure is formed by forming a reverse emitter window over the intrinsic base region, which subsequently is etched to form an emitter window having a multi-layer reverse insulating spacer therein.
摘要翻译：一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，集电极区域上的化合物半导体材料的本征基极区域，非本征基极区域，发射极结构，层间电介质层集电极区域，非本征基极区域和发射极结构以及通过层间介质层到基极区域，发射极结构和集电极区域的连接。通过在本征基极区域上形成反向发射极窗口形成发射极结构，其随后被蚀刻以形成其中具有多层反向绝缘间隔物的发射极窗口。

155. 发明授权

US06962850B2 Process to manufacture nonvolatile MOS memory device 有权
公开(公告)号：US06962850B2
公开(公告)日：2005-11-08
申请号：US10676896
申请日：2003-10-01
申请人： Vincent Ho , Wee Kiong Choi , Lap Chan , Wai Kin Chim , Vivian Ng , Cheng Lin Heng , Lee Wee Teo
发明人： Vincent Ho , Wee Kiong Choi , Lap Chan , Wai Kin Chim , Vivian Ng , Cheng Lin Heng , Lee Wee Teo
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/423 , H01L29/788
CPC分类号： B82Y10/00 , H01L21/28282 , H01L29/42332 , H01L29/7881 , Y10S438/962
摘要： Devices with embedded silicon or germanium nanocrystals, fabricated using ion implantation, exhibit superior data-retention characteristics relative to conventional floating-gate devices. However, the prior art use of ion implantation for their manufacture introduces several problems. These have been overcome by initial use of rapid thermal oxidation to grow a high quality layer of thin tunnel oxide. Chemical vapor deposition is then used to deposit a germanium doped oxide layer. A capping oxide is then deposited following which the structure is rapid thermally annealed to synthesize the germanium nanocrystals.

156. 发明授权

US06899857B2 Method for forming a region of low dielectric constant nanoporous material using a microemulsion technique 有权
标题翻译：使用微乳液技术形成低介电常数纳米多孔材料区域的方法
公开(公告)号：US06899857B2
公开(公告)日：2005-05-31
申请号：US10012298
申请日：2001-11-13
申请人： Soo Choi Pheng , Lap Chan , Wang Cui Yang , Siew Yong Kong , Alex See
发明人： Soo Choi Pheng , Lap Chan , Wang Cui Yang , Siew Yong Kong , Alex See
IPC分类号： C08J9/28 , H01L21/316 , H01L21/768 , C01B33/12 , C03C3/00 , C04B35/14 , C04B38/00
CPC分类号： C08J9/28 , C08J2201/0504 , C08J2383/00 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/31695 , H01L21/7682
摘要： A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of preparing a microemulsion. The method of the present embodiment then recites applying the microemulsion to a surface above which it is desired to form a region of low dielectric constant nanoporous material. Next, the present method recites subjecting the microemulsion, which has been applied to the surface, to a thermal process such that the region of low dielectric constant nanoporous material is formed above the surface.
摘要翻译：公开了一种形成低介电常数纳米多孔材料区域的方法。在一个实施方案中，本发明的方法包括制备微乳液的步骤。本实施例的方法然后将微乳液应用于其上希望形成低介电常数纳米多孔材料区域的表面。接下来，本方法叙述了将施加到表面的微乳液进行热处理，使得低介电常数纳米多孔材料的区域形成在表面上方。

157. 发明授权

US06890854B2 Method and apparatus for performing nickel salicidation 失效
标题翻译：用于进行镍盐化的方法和装置
公开(公告)号：US06890854B2
公开(公告)日：2005-05-10
申请号：US09726903
申请日：2000-11-29
申请人： Pooi See Lee , Kin Leong Pey , Alex See , Lap Chan
发明人： Pooi See Lee , Kin Leong Pey , Alex See , Lap Chan
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L29/49 , H01L21/26
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L29/4933
摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.
摘要翻译：公开了一种用于进行镍盐化的方法和装置。镍硅化物工艺通常包括：形成包括部分制造的集成电路部件和硅衬底的处理衬底; 将氮气掺入经处理的基底中; 将镍沉积在经处理的基底上; 对经处理的基板退火以形成单一硅化镍; 去除未反应的镍; 并执行串联程序来完成集成电路制造。该镍硅化物工艺增加了退火温度范围，通过盐化可在硅上形成连续的薄镍单硅化物层。它还延迟了单一硅化镍薄膜的聚集开始到更高的退火温度。此外，该镍硅化物工艺延迟了从单一硅化镍到更高电阻率的二硅化镍的转变到更高的退火温度。它还减少了镍增强的多晶硅晶粒生长，以防止层反转。这种镍硅化物工艺的一些实施例可以用于另外标准的自对准硅化物工艺中，以形成具有低电阻率晶体管栅电极和源极/漏极接触的集成电路器件。

158. 发明授权

US06878623B2 Technique to achieve thick silicide film for ultra-shallow junctions 失效
标题翻译：实现超浅结的厚硅化物薄膜技术
公开(公告)号：US06878623B2
公开(公告)日：2005-04-12
申请号：US10457885
申请日：2003-06-09
申请人： Cheng Cheh Tan , Randall Cher Liang Cha , Alex See , Lap Chan
发明人： Cheng Cheh Tan , Randall Cher Liang Cha , Alex See , Lap Chan
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L29/66507 , H01L29/41783 , H01L29/665 , H01L29/6656
摘要： A gate structure having associated (LDD) regions and source and drain is formed as is conventional. A first oxide spacer, for example, is formed along the sidewalls of the gate structure. A layer of metal such as titanium is then deposited over the surface of the gate structure. Second sidewall spacers are formed covering the metal over the first sidewall spacer and covering the metal over isolation regions. A layer of polysilicon is deposited over the surface of the gate structure. A rapid thermal annealing (RTA) is performed causing the metal to react with both the silicon in the junction below the metal and the polysilicon above the metal forming a metal silicide. Metal along the sidewalls between the first and second sidewall spacers and over the isolation regions does not react and is etched away. By providing an additional source of silicon in the polysilicon layer above the metal, a thicker silicide is achieved.
摘要翻译：具有相关联（LDD）区域和源极和漏极的栅极结构如常规形成。例如，沿着栅极结构的侧壁形成第一氧化物间隔物。然后在栅极结构的表面上沉积诸如钛的金属层。形成第二侧壁间隔物，覆盖第一侧壁间隔物上的金属，并将金属覆盖在隔离区上。在栅极结构的表面上沉积多晶硅层。进行快速热退火（RTA），使得金属与金属之下的结中的硅和形成金属硅化物的金属上方的多晶硅反应。沿着第一和第二侧壁间隔物之间的侧壁以及隔离区域上的金属不会反应并被蚀刻掉。通过在金属上方的多晶硅层中提供附加的硅源，可获得更厚的硅化物。

159. 发明授权

US06869884B2 Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 失效
标题翻译：通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程
公开(公告)号：US06869884B2
公开(公告)日：2005-03-22
申请号：US10225828
申请日：2002-08-22
申请人： Lap Chan , Sanford Chu , Chit Hwei Ng , Purakh Verma , Jia Zhen Zheng , Johnny Chew , Choon Beng Sia
发明人： Lap Chan , Sanford Chu , Chit Hwei Ng , Purakh Verma , Jia Zhen Zheng , Johnny Chew , Choon Beng Sia
IPC分类号： H01L21/20 , H01L21/265 , H01L21/302 , H01L21/461 , H01L21/764
CPC分类号： H01L21/764 , H01L21/26506
摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.
摘要翻译：降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。在所述至少一个上介电层上形成钝化层。图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

160. 发明申请

US20050059216A1 METHOD OF MAKING DIRECT CONTACT ON GATE BY USING DIELECTRIC STOP LAYER 失效
标题翻译：通过使用介质停止层在门上制造直接接触的方法
公开(公告)号：US20050059216A1
公开(公告)日：2005-03-17
申请号：US10664211
申请日：2003-09-17
申请人： Purakh Verma , Sanford Chu , Lap Chan , Yelehanka Ramachandramurthy Pradeep , Kai Shao , Jia Zheng
发明人： Purakh Verma , Sanford Chu , Lap Chan , Yelehanka Ramachandramurthy Pradeep , Kai Shao , Jia Zheng
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/84 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (f.,), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作时的噪声性能，增加的单位功率增益频率（f。）和减小的栅极延迟。

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