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131. 发明授权

US08304839B2 Poly resistor and poly eFuse design for replacement gate technology 有权
公开(公告)号：US08304839B2
公开(公告)日：2012-11-06
申请号：US13216114
申请日：2011-08-23
申请人： Kong-Beng Thei , Harry Chuang
发明人： Kong-Beng Thei , Harry Chuang
IPC分类号： H01L27/11
CPC分类号： H01L27/0629 , H01L23/5256 , H01L28/20 , H01L29/66545 , H01L29/66628 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Methods for fabricating a semiconductor device are disclosed. In an example, a method includes forming an isolation region on a substrate, wherein the isolation region extends a depth into the substrate from a substrate surface; forming a recess in the isolation region, wherein the recess is defined by a concave surface of the isolation region; and forming a first gate structure over the substrate surface and a second gate structure over the concave surface of the isolation region.

132. 发明授权

US08125051B2 Device layout for gate last process 有权
标题翻译：门最后进程的设备布局
公开(公告)号：US08125051B2
公开(公告)日：2012-02-28
申请号：US12471091
申请日：2009-05-22
申请人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu , Tzung-Chi Lee
发明人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu , Tzung-Chi Lee
IPC分类号： H01L27/06 , H01L21/70 , H01L21/338 , H01L21/302
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/0629 , H01L27/0635
摘要： A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，形成在第二区域中的隔离结构，形成在隔离结构中的至少一个接合器件第二区域，以及形成在第二区域中的隔离结构上方的停止结构。

133. 发明申请

US20120025329A1 Spacer Shape Engineering for Void-Free Gap-Filling Process 有权
标题翻译：无间隙填充过程的间隔形状工程
公开(公告)号：US20120025329A1
公开(公告)日：2012-02-02
申请号：US13270585
申请日：2011-10-11
申请人： Ming-Yuah Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuah Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/78
CPC分类号： H01L21/823481 , H01L21/823468 , H01L21/823475 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

134. 发明授权

US08093116B2 Method for N/P patterning in a gate last process 有权
标题翻译：最后一道工艺中N / P图案化的方法
公开(公告)号：US08093116B2
公开(公告)日：2012-01-10
申请号：US12364384
申请日：2009-02-02
申请人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/338
CPC分类号： H01L21/823842 , H01L21/28052 , H01L21/28088 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A method is provided that includes providing a substrate, forming a first gate structure in a first region and a second gate structure in a second region, the first and second gate structures each including a high-k dielectric layer, a silicon layer, and a hard mask layer, where the silicon layer of the first gate structure has a different thickness than the silicon layer of the second gate structure, forming an interlayer dielectric (ILD) over the first and second gate structures, performing a chemical mechanical polishing (CMP) on the ILD, removing the silicon layer from the first gate structure thereby forming a first trench, forming a first metal layer to fill in the first trench, removing the hard mask layer and the silicon layer from the second gate structure thereby forming a second trench, and forming a second metal layer to fill in the second trench.
摘要翻译：提供了一种方法，其包括提供衬底，在第一区域中形成第一栅极结构和在第二区域中形成第二栅极结构，所述第一和第二栅极结构各自包括高k电介质层，硅层和硬掩模层，其中第一栅极结构的硅层具有与第二栅极结构的硅层不同的厚度，在第一和第二栅极结构上形成层间电介质（ILD），执行化学机械抛光（CMP）在所述ILD上，从所述第一栅极结构去除所述硅层，从而形成第一沟槽，形成第一金属层以填充所述第一沟槽，从所述第二栅极结构去除所述硬掩模层和所述硅层，由此形成第二沟槽并且形成第二金属层以填充第二沟槽。

135. 发明申请

US20110303982A1 Resistive Device for High-K Metal Gate Technology and Method of Making the Same 有权
标题翻译：高K金属栅极技术的电阻装置及其制造方法
公开(公告)号：US20110303982A1
公开(公告)日：2011-12-15
申请号：US13216034
申请日：2011-08-23
申请人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L27/06
CPC分类号： H01L23/5256 , H01L21/823878 , H01L27/0629 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity.
摘要翻译：提供了一种半导体器件，其包括半导体衬底，形成在衬底中用于隔离衬底的有源区的隔离结构，隔离结构由第一材料形成，有源器件形成在衬底的有源区中，具有高k电介质和金属栅极的有源器件和形成在隔离结构中的无源器件，无源器件由不同于第一材料并具有预定电阻率的第二材料形成。

136. 发明申请

US20110233683A1 CHEMICAL MECHANICAL POLISHING (CMP) METHOD FOR GATE LAST PROCESS 有权
标题翻译：用于门控最后过程的化学机械抛光（CMP）方法
公开(公告)号：US20110233683A1
公开(公告)日：2011-09-29
申请号：US13156558
申请日：2011-06-09
申请人： Harry Chuang , Kong-Beng Thei , Su-Chen Lai , Gary Shen
发明人： Harry Chuang , Kong-Beng Thei , Su-Chen Lai , Gary Shen
IPC分类号： H01L27/092 , H01L29/772
CPC分类号： H01L21/823828 , H01L21/31053 , H01L21/823437 , H01L29/66545 , Y10S438/926
摘要： A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.
摘要翻译：提供了一种制造半导体器件的方法，其包括提供半导体衬底，形成多个晶体管，每个晶体管具有虚拟栅极结构，在包括虚拟栅极结构的衬底上形成接触蚀刻停止层（CESL），形成第一电介质层，以填充相邻虚拟栅极结构之间的每个区域的一部分，在CESL和第一介电层上形成化学机械抛光（CMP）阻挡层，在CMP停止层上形成第二介电层，对CMP 所述第二电介质层在所述CMP停止层处基本上停止，并且执行过度抛光以暴露所述伪栅极结构。

137. 发明授权

US07985690B2 Method for a gate last process 有权
标题翻译：最后一个进程的方法
公开(公告)号：US07985690B2
公开(公告)日：2011-07-26
申请号：US12478358
申请日：2009-06-04
申请人： Kong-Beng Thei , Harry Chuang , Su-Chen Lai , Gary Shen
发明人： Kong-Beng Thei , Harry Chuang , Su-Chen Lai , Gary Shen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L29/7833 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66583
摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括提供基板; 在所述衬底上形成一个或多个栅极结构; 在衬底上形成缓冲层，包括在一个或多个栅极结构上; 在缓冲层上形成蚀刻停止层; 在所述蚀刻停止层上形成层间电介质（ILD）层; 以及去除所述缓冲层的一部分，所述蚀刻停止层的一部分以及所述一个或多个栅极结构上的所述ILD层的一部分。

138. 发明申请

US20110177658A1 Standard Cell Architecture and Methods with Variable Design Rules 有权
标题翻译：具有可变设计规则的标准单元架构和方法
公开(公告)号：US20110177658A1
公开(公告)日：2011-07-21
申请号：US13074914
申请日：2011-03-29
申请人： Oscar M. K. Law , Manoj Achyutrao Joshi , Kong-Beng Thei , Harry Chuang
发明人： Oscar M. K. Law , Manoj Achyutrao Joshi , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/82
CPC分类号： H01L27/11807 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.
摘要翻译：公开了具有层与单元边界间隔的可变规则的标准单元布局的结构和方法。在一个实施例中，第一标准单元布局设置有导电层，其具有间隔最小间隔距离的至少两个部分，所述导电层具有至少一个与单元边界隔开的部分，第一间隔距离小于一半的最小间距; 与所述第一标准单元相邻设置的第二标准单元，所述第二单元中的所述导电层的至少一个第二部分与所述第一标准单元中的所述第一部分相邻设置，并且与所述第一标准单元间隔开第二间隔，最小其中所述第一和第二间距的总和至少与所述最小间隔一样大。公开了一种形成标准的方法。

139. 发明授权

US07981801B2 Chemical mechanical polishing (CMP) method for gate last process 有权
标题翻译：门最后工艺的化学机械抛光（CMP）方法
公开(公告)号：US07981801B2
公开(公告)日：2011-07-19
申请号：US12423422
申请日：2009-04-14
申请人： Harry Chuang , Kong-Beng Thei , Su-Chen Lai , Gary Shen
发明人： Harry Chuang , Kong-Beng Thei , Su-Chen Lai , Gary Shen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/823828 , H01L21/31053 , H01L21/823437 , H01L29/66545 , Y10S438/926
摘要： A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.
摘要翻译：提供了一种制造半导体器件的方法，其包括提供半导体衬底，形成多个晶体管，每个晶体管具有虚拟栅极结构，在包括虚拟栅极结构的衬底上形成接触蚀刻停止层（CESL），形成第一电介质层，以填充相邻虚拟栅极结构之间的每个区域的一部分，在CESL和第一介电层上形成化学机械抛光（CMP）阻挡层，在CMP停止层上形成第二介电层，对CMP 所述第二电介质层在所述CMP停止层处基本上停止，并且执行过度抛光以暴露所述伪栅极结构。

140. 发明授权

US07977754B2 Poly resistor and poly eFuse design for replacement gate technology 有权
标题翻译： Poly电阻和poly eFuse设计替代栅极技术
公开(公告)号：US07977754B2
公开(公告)日：2011-07-12
申请号：US12201602
申请日：2008-08-29
申请人： Harry Chuang , Kong-Beng Thei
发明人： Harry Chuang , Kong-Beng Thei
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L23/5256 , H01L28/20 , H01L29/66545 , H01L29/66628 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. The semiconductor device comprises a semiconductor substrate; an active region of the substrate, wherein the active region includes at least one transistor; and a passive region of the substrate, wherein the passive region includes at least one resistive structure disposed on an isolation region, the at least one resistive structure in a lower plane than the at least one transistor.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。半导体器件包括半导体衬底; 所述衬底的有源区，其中所述有源区包括至少一个晶体管; 和所述衬底的无源区域，其中所述无源区域包括设置在隔离区域上的至少一个电阻结构，所述至少一个电阻结构在比所述至少一个晶体管低的平面中。

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