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131. 发明授权

US07368354B2 Planar substrate devices integrated with FinFETs and method of manufacture 有权
标题翻译：与FinFET集成的平面衬底器件和制造方法
公开(公告)号：US07368354B2
公开(公告)日：2008-05-06
申请号：US11200271
申请日：2005-08-09
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823821 , H01L21/823828 , H01L21/823878 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A planar substrate device integrated with fin field effect transistors (FinFETs) and a method of manufacture comprises a silicon-on-insulator (SOI) wafer comprising a substrate; a buried insulator layer over the substrate; and a semiconductor layer over the buried insulator layer. The structure further comprises a FinFET over the buried insulator layer and a field effect transistor (FET) integrated in the substrate, wherein the FET gate is planar to the FinFET gate. The structure further comprises retrograde well regions configured in the substrate. In one embodiment, the structure further comprises a shallow trench isolation region configured in the substrate.
摘要翻译：与鳍状场效应晶体管（FinFET）集成的平面基板器件和制造方法包括：包括衬底的绝缘体上硅（SOI）晶片; 衬底上的掩埋绝缘体层; 以及掩埋绝缘体层上的半导体层。所述结构还包括在所述掩埋绝缘体层上的FinFET和集成在所述衬底中的场效应晶体管（FET），其中所述FET栅极与所述FinFET栅极平面。该结构还包括在衬底中配置的逆行阱区。在一个实施例中，该结构还包括在衬底中配置的浅沟槽隔离区域。

132. 发明授权

US07211356B2 Method of patterning a substrate by feeding mask defect data forward for subsequent correction 失效
标题翻译：通过将掩模缺陷数据向前馈入以进行后续校正来图案化衬底的方法
公开(公告)号：US07211356B2
公开(公告)日：2007-05-01
申请号：US11275178
申请日：2005-12-16
申请人： Jed H. Rankin , Andrew J. Watts
发明人： Jed H. Rankin , Andrew J. Watts
IPC分类号： G03C5/00
CPC分类号： G03F7/70466 , G03F1/70 , G03F1/72
摘要： A method is provided for patterning a substrate. In such method a first mask, for example, a front-end-of-line (“FEOL”) mask is fabricated, the first mask including a plurality of first features such as FEOL features which are usable to pattern regular elements and redundancy elements of a substrate such as a microelectronic substrate and/or a micro-electromechanical substrate. The first mask is tested, i.e., inspected for defects in the features. Thereafter, a second sequentially used mask, for example, a back-end-of-line (“BEOL”) mask is fabricated which includes a plurality of second features, e.g., BEOL features, such features being usable to pattern a plurality of interconnections between individual ones of the regular elements and between the regular elements and the redundancy elements. The regular elements and the redundancy elements are patterned using the first mask and the interconnections between them are patterned using the second mask. As a result, the interconnections are patterned in a way that corrects for the detected defects in the first mask.
摘要翻译：提供了用于图案化衬底的方法。在这种方法中，制造了第一掩模，例如前端（“FEOL”）掩模，第一掩模包括多个第一特征，例如可用于对规则元件和冗余元件进行图案的FEOL特征诸如微电子衬底和/或微机电衬底的衬底。测试第一个掩模，即检查特征中的缺陷。此后，制造第二顺序使用的掩模，例如，后端行（“BEOL”）掩模，其包括多个第二特征，例如BEOL特征，这样的特征可用于对多个互连在常规元素之间以及常规元素和冗余元素之间。使用第一掩模对常规元件和冗余元件进行图案化，并且使用第二掩模对它们之间的互连进行图案化。结果，互连以对第一掩模中检测到的缺陷进行校正的方式构图。

133. 发明授权

US07163864B1 Method of fabricating semiconductor side wall fin 有权
标题翻译：制造半导体侧壁翅片的方法
公开(公告)号：US07163864B1
公开(公告)日：2007-01-16
申请号：US09691353
申请日：2000-10-18
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.
摘要翻译：通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

134. 发明授权

US07064019B2 Implanted asymmetric doped polysilicon gate FinFET 有权
标题翻译：嵌入式不对称掺杂多晶硅栅极FinFET
公开(公告)号：US07064019B2
公开(公告)日：2006-06-20
申请号：US10869624
申请日：2004-06-16
申请人： David M. Fried , Edward J. Nowak , Jed H. Rankin
发明人： David M. Fried , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/84 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66795 , H01L2029/7858
摘要： An asymmetric field effect transistor (FET) that has a threshold voltage that is compatible with current CMOS circuit designs and a low resistive gate electrode is provided. Specifically, the asymmetric FET includes a p-type gate portion and an n-type gate portion on a vertical semiconductor body; an interconnect between the p-type gate portion and the n-type gate portion; and a planarizing structure above the interconnect.
摘要翻译：提供具有与当前CMOS电路设计兼容的阈值电压和低电阻栅电极的非对称场效应晶体管（FET）。具体地说，非对称FET在垂直半导体本体上包括p型栅极部分和n型栅极部分; p型栅极部分和n型栅极部分之间的互连; 以及互连上方的平坦化结构。

135. 发明授权

US06947275B1 Fin capacitor 失效
标题翻译：散热片电容
公开(公告)号：US06947275B1
公开(公告)日：2005-09-20
申请号：US10711975
申请日：2004-10-18
申请人： Brent A Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01G4/005 , H01G4/012 , H01G4/06 , H01G4/33 , H01L21/02 , H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/13
CPC分类号： H01G4/012 , H01G4/06 , H01G4/33 , H01L21/84 , H01L27/1085 , H01L27/13 , H01L28/92 , Y10T29/435
摘要： Disclosed is a capacitor structure and method for forming the same. This structure has a conductive substrate, conductive fins extending above the substrate, and trenches extending into the substrate. These trenches are positioned between locations where the fins extend above the substrate. The invention includes an insulator in the trenches and covering the fins. This insulator separates the substrate and fins from a conductive top plate that covers the fins and fills the trenches. A bottom plate contact electrically connects the fins and the substrate such that the fins and the substrate comprise a bottom plate of the capacitor structure.
摘要翻译：公开了一种电容器结构及其形成方法。该结构具有导电基板，在基板上方延伸的导电翅片和延伸到基板中的沟槽。这些沟槽位于翅片在衬底上方延伸的位置之间。本发明包括沟槽中的绝缘体并覆盖翅片。该绝缘体将基板和散热片与覆盖翅片的导电顶板隔开并填充沟槽。底板接触件电连接散热片和基板，使得散热片和基板包括电容器结构的底板。

136. 发明授权

US06573541B1 Charge coupled device with channel well 有权
标题翻译：电荷耦合器件通道良好
公开(公告)号：US06573541B1
公开(公告)日：2003-06-03
申请号：US09670595
申请日：2000-09-29
申请人： William A. Klaasen , Gary D. Pittman , Jed H. Rankin
发明人： William A. Klaasen , Gary D. Pittman , Jed H. Rankin
IPC分类号： H01L27148
CPC分类号： H01L29/76858 , H01L27/14887
摘要： A solid-state CCD device suitable for forming into arrays and for use with suitable hardware to form video image capture devices and methods for fabricating same are provided.
摘要翻译：提供了适合于形成阵列并与合适的硬件一起使用以形成视频图像捕获装置的固态CCD装置及其制造方法。

137. 发明授权

US06534389B1 Dual level contacts and method for forming 失效
标题翻译：双层接触和成型方法
公开(公告)号：US06534389B1
公开(公告)日：2003-03-18
申请号：US09521977
申请日：2000-03-09
申请人： Thomas G. Ference , Kurt R. Kimmel , Alain Loiseau , Jed H. Rankin
发明人： Thomas G. Ference , Kurt R. Kimmel , Alain Loiseau , Jed H. Rankin
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A method for making electrical contacts to device regions in a semiconductor substrate, and the resulting structure, is presented. A first set of borderless contacts is initially formed. This first set of contacts is then contacted by a second series of smaller, upper-level contacts. The second set of contacts also contact the gate of the device. The structure which results has a form wherein there are stacked contacts to the diffusion layer, and a single level contact to the device gate. The structure further provides local interconnectability over gate structures.
摘要翻译：提出了一种用于与半导体衬底中的器件区域进行电接触的方法及其结果。最初形成了第一套无边界接触。然后第一组联系人被第二系列较小的上层联系人联系起来。第二组触点也与设备的门接触。结果是具有与扩散层的堆叠接触的形式，以及与器件栅极的单级接触。该结构还提供了栅极结构上的局部互连性。

138. 发明授权

US06504207B1 Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same 失效
标题翻译：创建集成了高性能逻辑和NVRAM的EEPROM存储器结构的方法，以及与之相同的操作条件
公开(公告)号：US06504207B1
公开(公告)日：2003-01-07
申请号：US09609292
申请日：2000-06-30
申请人： Bomy A. Chen , Jay G. Harrington , Kevin M. Houlihan , Dennis Hoyniak , Chung Hon Lam , Hyun Koo Lee , Rebecca D. Mih , Jed H. Rankin
发明人： Bomy A. Chen , Jay G. Harrington , Kevin M. Houlihan , Dennis Hoyniak , Chung Hon Lam , Hyun Koo Lee , Rebecca D. Mih , Jed H. Rankin
IPC分类号： H01L2976
CPC分类号： H01L21/28273 , G11C16/0408 , H01L29/42328
摘要： A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.
摘要翻译：与高性能逻辑或NVRAM集成的EEPROM存储器件的方法和结构。 EEPROM器件包括浮置栅极和彼此自对准的程序栅极。在编程期间，在浮栅和程序门之间发生电子隧穿。

139. 发明授权

US06458630B1 Antifuse for use with low k dielectric foam insulators 失效
标题翻译：用于低k电介质泡沫绝缘子的防腐剂
公开(公告)号：US06458630B1
公开(公告)日：2002-10-01
申请号：US09417853
申请日：1999-10-14
申请人： Timothy H. Daubenspeck , William A. Klaasen , William T. Motsiff , Rosemary A. Previti-Kelly , Jed H. Rankin
发明人： Timothy H. Daubenspeck , William A. Klaasen , William T. Motsiff , Rosemary A. Previti-Kelly , Jed H. Rankin
IPC分类号： H01L2128
CPC分类号： H01L23/5254 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low k nanopore/nanofoam dielectric material adjacent the conductive line ends.
摘要翻译：用于半导体器件的可熔连接件包括在绝缘衬底的表面上的绝缘衬底和导电线对，导电线对具有间隔开的端部。聚合物设置在绝缘基板之上和导线对端之间。聚合物能够在暴露于能量束时从非导电状态改变为导电状态。优选地，聚合物包括聚酰亚胺，更优选聚合物/鎓盐混合物，最优选掺杂有三苯基鎓盐的聚苯胺聚合物。该连接可以进一步包括邻近导电线端部的低k纳米孔/纳米空间电介质材料。

140. 发明授权

US06261895B1 Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor 失效
标题翻译：具有大电容和低电阻的多晶硅电容器和用于形成电容器的工艺
公开(公告)号：US06261895B1
公开(公告)日：2001-07-17
申请号：US09225043
申请日：1999-01-04
申请人： James W. Adkisson , John A. Bracchitta , Jed H. Rankin , Anthony K. Stamper
发明人： James W. Adkisson , John A. Bracchitta , Jed H. Rankin , Anthony K. Stamper
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/3144 , H01L28/91
摘要： A process for forming capacitors in a semiconductor device. In one embodiment, a first insulating layer is deposited on the semiconductor device; a trench is formed in the insulating layer; a first low resistance metal layer is formed covering the interior surface of the trench; a first polysilicon layer is formed over the first low resistance metal layer; a first dielectric layer is formed over the first polysilicon layer; a second polysilicon layer is formed over the first dielectric layer; a second low resistance metal layer is formed over the second polysilicon layer; a third polysilicon layer is formed over the second low resistance metal layer; a second dielectric layer is formed over the third polysilicon layer; a fourth polysilicon layer is formed over the second dielectric layer; a third low resistance metal layer is formed over the fourth polysilicon layer until the trench is filled; the semiconductor device is planarized until the first, second and third low resistance metal layers are exposed above the trench; finally, capacitor leads are formed to the first, second, and third low resistance metal layers.
摘要翻译：一种用于在半导体器件中形成电容器的工艺。在一个实施例中，第一绝缘层沉积在半导体器件上; 在绝缘层中形成沟槽; 形成覆盖沟槽内表面的第一低电阻金属层; 在第一低电阻金属层上形成第一多晶硅层; 第一介电层形成在第一多晶硅层上; 在第一介电层上形成第二多晶硅层; 在第二多晶硅层上形成第二低电阻金属层; 在第二低电阻金属层上形成第三多晶硅层; 在所述第三多晶硅层上形成第二电介质层; 在第二介电层上形成第四多晶硅层; 第四低电阻金属层形成在第四多晶硅层上，直到沟槽被填充; 半导体器件被平坦化，直到第一，第二和第三低电阻金属层暴露在沟槽上方; 最后，对第一，第二和第三低电阻金属层形成电容器引线。

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