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1. 发明授权

US06504207B1 Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same 失效
标题翻译：创建集成了高性能逻辑和NVRAM的EEPROM存储器结构的方法，以及与之相同的操作条件
公开(公告)号：US06504207B1
公开(公告)日：2003-01-07
申请号：US09609292
申请日：2000-06-30
申请人： Bomy A. Chen , Jay G. Harrington , Kevin M. Houlihan , Dennis Hoyniak , Chung Hon Lam , Hyun Koo Lee , Rebecca D. Mih , Jed H. Rankin
发明人： Bomy A. Chen , Jay G. Harrington , Kevin M. Houlihan , Dennis Hoyniak , Chung Hon Lam , Hyun Koo Lee , Rebecca D. Mih , Jed H. Rankin
IPC分类号： H01L2976
CPC分类号： H01L21/28273 , G11C16/0408 , H01L29/42328
摘要： A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.
摘要翻译：与高性能逻辑或NVRAM集成的EEPROM存储器件的方法和结构。 EEPROM器件包括浮置栅极和彼此自对准的程序栅极。在编程期间，在浮栅和程序门之间发生电子隧穿。

2. 发明授权

US06326275B1 DRAM cell with vertical CMOS transistor 有权
标题翻译：具有垂直CMOS晶体管的DRAM单元
公开(公告)号：US06326275B1
公开(公告)日：2001-12-04
申请号：US09559363
申请日：2000-04-24
申请人： Jay G. Harrington , David V. Horak , Kevin M. Houlihan , Chung Hon Lam , Rebecca D. Mih
发明人： Jay G. Harrington , David V. Horak , Kevin M. Houlihan , Chung Hon Lam , Rebecca D. Mih
IPC分类号： H01L2120
CPC分类号： H01L27/10867 , H01L27/10864
摘要： A DRAM memory cell having a trench capacitor includes a vertical pass transistor formed in the top of the trench in a process that forms a doped poly protective layer on the upper sidewalls above a sacrificial intrinsic poly spacer layer, the doped poly protecting the sidewalls while the intrinsic poly spacer layer is removed and replaced with a conductive strap layer that both forms a strap from the capacitor electrode and serves as a source of dopant to form a transistor electrode in the silicon substrate; the protective layer and the upper portion of the strap material being removed simultaneously so that no extra step is required; after which the trench walls are oxidized to form the transistor gate dielectric and conductive material is deposited to form the wordline and the gates for the vertical transistors simultaneously.
摘要翻译：具有沟槽电容器的DRAM存储单元包括形成在沟槽顶部的垂直传输晶体管，该工艺在牺牲本征聚间隔层上方的上侧壁上形成掺杂的多晶保护层，掺杂的多晶硅保护侧壁，而本征聚间隔层被去除并被导电带层替代，导电带层都形成来自电容器电极的带，并且用作掺杂剂源以在硅衬底中形成晶体管电极; 保护层和带材的上部被同时移除，使得不需要额外的步骤; 之后，沟槽壁被氧化以形成晶体管栅极电介质并且沉积导电材料以同时形成用于垂直晶体管的字线和栅极。

3. 发明授权

US6132940A Method for producing constant profile sidewalls 失效
标题翻译：制造恒定型材侧壁的方法
公开(公告)号：US6132940A
公开(公告)日：2000-10-17
申请号：US213028
申请日：1998-12-16
申请人： Rebecca D. Mih , Franz X. Zach
发明人： Rebecca D. Mih , Franz X. Zach
IPC分类号： G03F7/00 , G03F7/20
CPC分类号： G03F7/2024 , G03F7/00 , G03F7/2022
摘要： A method of making at least one feature on an object having an upper surface, comprising the steps of:1. applying a layer of a photoresist having an initial thickness to the upper surface;2. exposing the layer of photoresist to a first dosage of light having a first intensity for a first predetermined period of time, such that at least a portion of the upper surface has a thickness that is at most equal to the initial thickness; and3. exposing the layer of photoresist to a second dosage of light having a second intensity for a second predetermined period of time, such that at least a subset of the portion of the upper surface exposed by the first dosage of light is exposed by the second dosage of light.
摘要翻译：一种在具有上表面的物体上制造至少一个特征的方法，包括以下步骤：1.将具有初始厚度的光致抗蚀剂层施加到上表面; 2.将光致抗蚀剂层暴露于具有第一强度的第一剂量的光，持续第一预定时间段，使得上表面的至少一部分具有最大等于初始厚度的厚度; 以及3.将所述光致抗蚀剂层暴露于具有第二强度的第二剂量的光，持续第二预定时间段，使得由所述第一剂量的光暴露的所述上表面部分的至少一部分被所述第第二剂量的光。

4. 发明授权

US06448629B2 Semiconductor device and method of making same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06448629B2
公开(公告)日：2002-09-10
申请号：US09354742
申请日：1999-07-29
申请人： Rebecca D. Mih , Kevin S. Petrarca
发明人： Rebecca D. Mih , Kevin S. Petrarca
IPC分类号： H01L2906
CPC分类号： H01L21/0332 , H01L21/76224 , H01L21/7684
摘要： A second or cap dielectric layer is interposed between the usual or base dielectric layer and the metallic circuitry layer of a semiconductor device. The base dielectric layer has a plurality of recesses in an inactive part of the semiconductor device into which parts of the cap dielectric layer extend to interlock the cap dielectric layer to the base dielectric layer and to oppose shearing or tearing of the either (1) the metallic circuitry layer as the metallic circuitry layer is subjected to chemical-mechanical polishing, or (2) a hard mask layer from the base dielectric layer as the metallic circuitry layer is subjected to chemical-mechanical polishing.
摘要翻译：第二或盖电介质层介于通常的或基底电介质层与半导体器件的金属电路层之间。基极电介质层在半导体器件的非活性部分中具有多个凹部，盖电介质层的部分延伸以将盖电介质层与基底电介质层互锁，并且相对于（1）的剪切或撕裂金属电路层作为金属电路层进行化学机械抛光，或（2）当金属电路层进行化学机械抛光时，从基极介电层获得硬掩模层。

5. 发明授权

US06391703B1 Buried strap for DRAM using junction isolation technique 失效
标题翻译：使用结隔离技术的DRAM埋地带
公开(公告)号：US06391703B1
公开(公告)日：2002-05-21
申请号：US09894336
申请日：2001-06-28
申请人： Nivo Rovedo , Chung H. Lam , Rebecca D. Mih
发明人： Nivo Rovedo , Chung H. Lam , Rebecca D. Mih
IPC分类号： H01L218242
CPC分类号： H01L27/10867
摘要： A logic circuit including an embedded DRAM achieves process integration by simultaneously forming the strap connecting the memory cell capacitor with the pass transistor and a buried dielectric layer isolating the logic transistor sources and drains from the substrate.
摘要翻译：包括嵌入式DRAM的逻辑电路通过同时形成将存储单元电容器与传输晶体管连接的带以及将逻辑晶体管源极和漏极与衬底隔离的埋入介质层来实现工艺集成。

6. 发明授权

US06284574B1 Method of producing heat dissipating structure for semiconductor devices 失效
标题翻译：制造半导体器件散热结构的方法
公开(公告)号：US06284574B1
公开(公告)日：2001-09-04
申请号：US09223979
申请日：1999-01-04
申请人： Kevin Shawn Petrarca , Sarah Knickerbocker , Joyce C. Liu , Rebecca D. Mih
发明人： Kevin Shawn Petrarca , Sarah Knickerbocker , Joyce C. Liu , Rebecca D. Mih
IPC分类号： H01L2148
CPC分类号： H01L23/36 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： A structure and process are described for facilitating the conduction of heat away from a semiconductor device. Thermally conductive planes and columns are incorporated within the back-end structure and around the interconnect outside the chip. A thermally conductive plane is formed by forming a first insulating layer on an underlying layer of the device; forming a recess in the insulating layer; filling the recess with a thermally conductive material to form a lateral heat-dissipating layer; planarizing the heat-dissipating layer to make the top surface thereof coplanar with the unrecessed portion of the insulating layer; and forming a second insulating layer on the first insulating layer and the heat-dissipating layer, thereby embedding the heat-dissipating layer between the first and second insulating layers. The heat-dissipating layer is electrically isolated from the underlying layer of the device, and preferably is electrically grounded.
摘要翻译：描述了用于促进远离半导体器件的热传导的结构和工艺。导热平面和列结合在后端结构中并且围绕芯片外的互连。导热平面通过在器件的下层上形成第一绝缘层而形成; 在所述绝缘层中形成凹部; 用导热材料填充凹部以形成横向散热层; 使散热层平坦化，使其顶面与绝缘层的未加工部分共面; 以及在所述第一绝缘层和所述散热层上形成第二绝缘层，从而将所述散热层嵌入所述第一绝缘层和所述第二绝缘层之间。散热层与器件的下层电隔离，优选电接地。

7. 发明申请

US20120040277A1 DAMASCENE RETICLE AND METHOD OF MANUFACTURE THEREOF 失效
标题翻译：大理石制品及其制造方法
公开(公告)号：US20120040277A1
公开(公告)日：2012-02-16
申请号：US13278571
申请日：2011-10-21
申请人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
发明人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
IPC分类号： G03F1/00 , B24B41/06
CPC分类号： G03F1/00 , G03F1/26 , G03F1/50
摘要： A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.
摘要翻译：用于能够容纳标线的抛光工具的掩模版载体包括具有正面和反面的基板，固定在基板的正面的保持环，形成由刚性基板的正面限定的凹部和内部固定环的边缘。掩模垫在凹槽中支撑掩模版。基板和标线垫具有一组匹配的对准的通孔，用于从底板和标线板之间的空间排出空气，并将空气供给到该空间，因此真空可以将该掩模版保持在适当的位置上在真空条件下的掩模版载体和在压力下施加空气可以从掩模版载体喷出掩模版。

8. 发明申请

US20080286660A1 DAMASCENE RETICLE AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：大理石制品及其制造方法
公开(公告)号：US20080286660A1
公开(公告)日：2008-11-20
申请号：US11749384
申请日：2007-05-16
申请人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
发明人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
IPC分类号： G03F1/00 , C09K3/14
CPC分类号： G03F1/00 , G03F1/26 , G03F1/50
摘要： A method for manufacturing an optical projection reticle employs a damascene process. First feature recesses are etched into a projection reticle mask plate which is transmissive or transparent. Then feature recesses are tilled with a radiation transmissivity modifying material comprising a partially transmissive material and/or a radiation absorber for absorbing actinic radiation. Sacrificial materials may be added to the recess temporarily prior to filling the recess to provide gaps juxtaposed with the material filling the recess. Thereafter, the sacrificial materials are removed. Then the projection mask is planarized leaving feature recesses filled with transmissivity modifying material, and any gaps desired. The projection mask is planarized while retained in a fixture holding it in place during polishing with a polishing tool and a slurry.
摘要翻译：光学投影掩模版的制造方法采用镶嵌工艺。第一特征凹槽被蚀刻到透射或透明的突出掩模掩模板中。然后，特征凹部用包括用于吸收光化辐射的部分透射材料和/或辐射吸收体的辐射透射率改性材料研磨。牺牲材料可以在填充凹部之前临时添加到凹部中，以提供与填充凹部的材料并置的间隙。此后，去除牺牲材料。然后将投影掩模平坦化，留下填充有透射率改性材料的特征凹部，以及任何期望的间隙。投影面罩被平坦化，同时保持在用抛光工具和浆料抛光过程中将其固定在位置的夹具中。

9. 发明授权

US08439728B2 Reticle carrier 失效
标题翻译：标线载体
公开(公告)号：US08439728B2
公开(公告)日：2013-05-14
申请号：US13278571
申请日：2011-10-21
申请人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
发明人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
IPC分类号： B24B41/06
CPC分类号： G03F1/00 , G03F1/26 , G03F1/50
摘要： A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.
摘要翻译：用于能够容纳标线的抛光工具的掩模版载体包括具有正面和反面的基板，固定在基板的正面的保持环，形成由刚性基板的正面限定的凹部和内部固定环的边缘。掩模垫在凹槽中支撑掩模版。基板和标线垫具有一组匹配的对准的通孔，用于从底板和标线板之间的空间排出空气，并将空气供给到该空间，因此真空可以将该掩模版保持在适当的位置上在真空条件下的掩模版载体和在压力下施加空气可以从掩模版载体喷出掩模版。

10. 发明授权

US06407396B1 Wafer metrology structure 有权
标题翻译：晶圆计量结构
公开(公告)号：US06407396B1
公开(公告)日：2002-06-18
申请号：US09339783
申请日：1999-06-24
申请人： Rebecca D. Mih , Eric P. Solecky , Donald C. Wheeler
发明人： Rebecca D. Mih , Eric P. Solecky , Donald C. Wheeler
IPC分类号： H01J37304
CPC分类号： G03F7/70625 , G03F7/70633 , H01J2237/2816 , H01L22/34
摘要： A wafer metrology structure for measuring both critical dimension features of multiple patterns of a semiconductor device and overlay measurements of one pattern with respect to another. The measurements are readable by a single, one-dimensional scan of a metrology system. The wafer metrology structure includes at least a first feature of a first dimension formed in a first level of the semiconductor device. The first dimension is identical to a first critical dimension of a pattern formed in the corresponding first level. A wafer metrology pattern according to the present invention also includes a second pattern of a second dimension formed in a second level of the semiconductor device. The second pattern includes an aperture superposed over the first feature. The aperture exposes at least the first feature having a critical dimension of the first pattern and thus enables a metrology system to directly measure the first feature through the aperture. The second pattern also includes a feature having a second dimension identical to a second critical dimension of the second pattern formed in the corresponding second level.
摘要翻译：一种用于测量半导体器件的多个图案的关键尺寸特征并且相对于另一个图案叠加测量一个图案的晶片度量结构。测量可以通过计量系统的单一一维扫描来读取。晶片计量结构包括形成在半导体器件的第一级中的至少第一尺寸的第一特征。第一尺寸与在相应的第一层中形成的图案的第一临界尺寸相同。根据本发明的晶片测量图案还包括形成在半导体器件的第二级中的第二尺寸的第二图案。第二图案包括叠加在第一特征上的光圈。孔径至少暴露出具有第一图案的临界尺寸的第一特征，从而使计量系统能够通过孔直接测量第一特征。第二图案还包括具有与在相应的第二层中形成的第二图案的第二临界尺寸相同的第二尺寸的特征。

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