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121. 发明申请

US20050098834A1 HETEROJUNCTION BICMOS SEMICONDUCTOR 失效
标题翻译：异常BICMOS半导体
公开(公告)号：US20050098834A1
公开(公告)日：2005-05-12
申请号：US10705163
申请日：2003-11-06
申请人： Jia Zheng , Lap Chan , Shao-fu Chu
发明人： Jia Zheng , Lap Chan , Shao-fu Chu
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/108 , H01L21/8238 , H01L29/04
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623
摘要： A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.
摘要翻译：因此，提供BiCMOS半导体及其制造方法。提供具有集电极区域的半导体衬底。在集电极区域上形成伪栅极。在伪栅极中形成发射器窗口以形成外部基极结构。在伪栅极的一部分下面的底切区域形成为在底切区域中提供内部基极结构。发射极结构在内部基极结构的发射极窗口中形成。在半导体衬底上形成层间电介质层，并且通过层间电介质层到集电极区域，非本征基极结构和发射极结构形成连接。本征基础结构包括诸如硅和硅 - 锗的复合半导体材料或硅 - 锗 - 碳或其组合。

122. 发明申请

US20050079678A1 Heterojunction bipolar transistor using reverse emitter window 有权
标题翻译：使用反向发射极窗口的异质结双极晶体管
公开(公告)号：US20050079678A1
公开(公告)日：2005-04-14
申请号：US10683713
申请日：2003-10-09
申请人： Purakh Verma , Shao-Fu Chu , Lap Chan , Jian Li , Jia Zheng
发明人： Purakh Verma , Shao-Fu Chu , Lap Chan , Jian Li , Jia Zheng
IPC分类号： H01L21/331 , H01L29/08 , H01L29/417 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/41708 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, an intrinsic base region of a compound semiconductive material over the collector region, an extrinsic base region, an emitter structure, an interlevel dielectric layer over the collector region, extrinsic base region and emitter structure, and connections through the interlevel dielectric layer to the base region, the emitter structure, and the collector region. The emitter structure is formed by forming a reverse emitter window over the intrinsic base region, which subsequently is etched to form an emitter window having a multi-layer reverse insulating spacer therein.
摘要翻译：一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，集电极区域上的化合物半导体材料的本征基极区域，非本征基极区域，发射极结构，层间电介质层集电极区域，非本征基极区域和发射极结构以及通过层间介质层到基极区域，发射极结构和集电极区域的连接。通过在本征基极区域上形成反向发射极窗口形成发射极结构，其随后被蚀刻以形成其中具有多层反向绝缘间隔物的发射极窗口。

123. 发明授权

US06869857B2 Method to achieve STI planarization 失效
标题翻译：实现STI平坦化的方法
公开(公告)号：US06869857B2
公开(公告)日：2005-03-22
申请号：US10002987
申请日：2001-11-30
申请人： Feng Dai , Pang Choong Hau , Peter Hing , Lap Chan
发明人： Feng Dai , Pang Choong Hau , Peter Hing , Lap Chan
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , H01L21/31055 , H01L21/31056
摘要： A new method of forming shallow trench isolations without using CMP is described. A plurality of isolation trenches are etched through an etch stop layer into the semiconductor substrate leaving narrow and wide active areas between the trenches. An oxide layer is deposited over the etch stop layer and within the trenches using a high density plasma chemical vapor deposition process (HDP-CVD) having a deposition component and a sputtering component wherein after the oxide layer fills the trenches, the deposition component is discontinued while continuing the sputtering component until the oxide layer is at a desired depth. In one method, the oxide layer overlying the etch stop layer in the wide active areas is etched away. The etch stop layer and oxide layer residues are removed to complete planarized STI regions. In another method, a second etch stop layer is deposited over the oxide layer using a HDP-CVD process whereby the second etch stop layer is sputtered away over the oxide layer overlying the first etch stop layer in the narrow active areas and whereby the second etch stop layer remains in the wide active areas. The second etch stop layer over the oxide layer in the wide active areas is etched away. The oxide layer overlying the first etch stop layer in the narrow and wide active areas is etched away. The first and second etch stop layers are removed to complete STI regions.
摘要翻译：描述了不使用CMP形成浅沟槽隔离的新方法。通过蚀刻停止层将多个隔离沟槽蚀刻到半导体衬底中，在沟槽之间留下窄而宽的有源区。使用具有沉积组分和溅射组分的高密度等离子体化学气相沉积工艺（HDP-CVD），在蚀刻停止层和沟槽内沉积氧化物层，其中在氧化物层填充沟槽之后，沉积组分被中断同时继续溅射组分直到氧化物层处于期望的深度。在一种方法中，覆盖在宽有效区域中的蚀刻停止层上的氧化物层被蚀刻掉。去除蚀刻停止层和氧化物层残余物以完成平坦化的STI区域。在另一种方法中，使用HDP-CVD工艺在氧化物层上沉积第二蚀刻停止层，由此将第二蚀刻停止层溅射在覆盖窄有源区域中的第一蚀刻停止层上的氧化物层上，并且由此第二蚀刻停止层保留在广泛的有效区域。在宽的有源区域中的氧化物层上的第二蚀刻停止层被蚀刻掉。覆盖在窄且宽的有源区域中的第一蚀刻停止层上的氧化物层被蚀刻掉。去除第一和第二蚀刻停止层以完成STI区域。

124. 发明授权

US06730571B1 Method to form a cross network of air gaps within IMD layer 失效
标题翻译：在IMD层内形成气隙交叉网络的方法
公开(公告)号：US06730571B1
公开(公告)日：2004-05-04
申请号：US09418029
申请日：1999-10-14
申请人： Lap Chan , Cher Liang Cha , Kheng Chok Tee
发明人： Lap Chan , Cher Liang Cha , Kheng Chok Tee
IPC分类号： H01L21331
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In accordance with the objectives of the invention a new method is provided for creating air gaps in a layer of IMD. First and second layers of dielectric are successively deposited over a surface; the surface contains metal lines running in an Y-direction. Trenches are etched in the first and second layer of dielectric in an X and Y-direction respectively. The trenches are filled with a layer of nitride and polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. Openings are created through the thin layer of oxide that align with the points of intersect of the nitride in the trenches in the layers of dielectric. The nitride is removed from the trenches by a wet etch, thereby opening trenches in the layers of dielectric with both sets of trenches being interconnected. The openings in the thin layer of oxide are closed, leaving a network of trenches containing air in the two layers of dielectric.
摘要翻译：根据本发明的目的，提供了一种用于在IMD层中产生气隙的新方法。第一和第二层电介质依次沉积在表面上; 表面包含沿Y方向延伸的金属线。在第一和第二电介质层中分别在X和Y方向上蚀刻沟槽。沟槽填充有一层氮化物并抛光。在第二电介质层的表面上沉积薄层的氧化物。通过与电介质层中的沟槽中的氮化物的交叉点对准的氧化物薄层产生开口。通过湿蚀刻从沟槽中去除氮化物，从而在两组沟槽互连的情况下打开电介质层中的沟槽。氧化物薄层中的开口是封闭的，留下在两层电介质中含有空气的沟槽网络。

125. 发明授权

US06638844B1 Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill 有权
标题翻译：通过背面沟槽和填充来减少半导体技术中射频CMOS（RFCMOS）器件的衬底耦合/噪声的方法
公开(公告)号：US06638844B1
公开(公告)日：2003-10-28
申请号：US10207549
申请日：2002-07-29
申请人： Purakh Raj Verma , Sanford Chu , Chit Hwei , Lap Chan
发明人： Purakh Raj Verma , Sanford Chu , Chit Hwei , Lap Chan
IPC分类号： H01L2144
CPC分类号： H01L27/08 , H01L21/76224 , H01L21/823878 , H01L27/0617
摘要： A method of reducing substrate coupling and noise for one or more RFCMOS components comprising the following steps. A substrate having a frontside and a backside is provided. One or more RFCMOS components are formed over the substrate. One or more isolation structures are formed within the substrate proximate the one or more RFCOMS components. The backside of the substrate is etched to form respective trenches within the substrate and over at least the one or more isolation structures. The respective trenches are filled with dielectric material whereby the substrate coupling and noise for the one or more RFCMOS components are reduced.
摘要翻译：一种降低一个或多个RFCMOS组件的衬底耦合和噪声的方法，包括以下步骤。提供具有前侧和背侧的基板。在衬底上形成一个或多个RFCMOS部件。一个或多个隔离结构在靠近一个或多个RFCOMS组件的衬底内形成。蚀刻衬底的背面以在衬底内并且在至少一个或多个隔离结构上形成相应的沟槽。相应的沟槽被电介质材料填充，由此降低了一个或多个RFCMOS部件的衬底耦合和噪声。

126. 发明授权

US06461900B1 Method to form a self-aligned CMOS inverter using vertical device integration 失效
标题翻译：使用垂直器件集成形成自对准CMOS反相器的方法
公开(公告)号：US06461900B1
公开(公告)日：2002-10-08
申请号：US09981438
申请日：2001-10-18
申请人： Ravi Sundaresan , Yang Pan , James Lee Young Meng , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek
发明人： Ravi Sundaresan , Yang Pan , James Lee Young Meng , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek
IPC分类号： H01L2100
CPC分类号： H01L21/84 , H01L21/823885 , H01L27/1203
摘要： A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprises silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.
摘要翻译：实现了在集成电路器件中形成紧密间隔的垂直NMOS和PMOS晶体管对的方法。衬底包括硅注入氧化物（SIMOX），其中氧化物层夹在下层和上层的硅层之间。离子选择性地注入到上覆硅层的第一部分中以形成用于NMOS晶体管的漏极，沟道区和源极。漏极直接形成在氧化层的上方，沟道区形成在漏极上方，源极形成在沟道区域的上方。离子选择性地注入到上层硅层的第二部分中以形成用于PMOS晶体管的漏极，沟道区和源极。漏极直接形成在氧化层的上方，PMOS沟道区形成在漏极上方，源极形成在沟道区域的上方。 PMOS晶体管漏极与所述NMOS晶体管漏极接触。通过NMOS和PMOS源极和沟道区域蚀刻栅极沟槽。栅极沟槽在NMOS和PMOS漏极处终止并暴露NMOS和PMOS沟道区的侧壁。形成栅极氧化层，覆盖NMOS沟道区和PMOS沟道区，并衬在栅极沟槽。沉积多晶硅层并回蚀刻以形成多晶硅侧壁，从而形成用于紧密间隔的垂直NMOS和PMOS晶体管对的栅极。

127. 发明授权

US06461887B1 Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth 有权
标题翻译：通过蚀刻沉积蚀刻和选择性外延生长形成倒置阶梯STI结构的方法
公开(公告)号：US06461887B1
公开(公告)日：2002-10-08
申请号：US10038391
申请日：2002-01-03
申请人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
发明人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
IPC分类号： H01L2100
CPC分类号： H01L21/76232
摘要： A method of forming an inverted staircase shaped STI structure comprising the following steps. A semiconductor substrate having an overlying oxide layer is provided. The substrate having at least a pair of active areas defining an STI region therebetween. The oxide layer is etched a first time within the active areas to form first step trenches. The first step trenches having exposed sidewalls. Continuous side wall spacers are formed on said exposed first step trench sidewalls. The oxide layer is etched X+1 more successive times using the previously formed step side wall spacers as masks to form successive step trenches within the active areas. Each of the successive step trenches having exposed sidewalls and have side wall spacers successively formed on the successive step trench exposed sidewalls. The oxide layer is etched a final time using the previously formed step side wall spacers as masks to form final step trenches exposing the substrate within the active areas. The STI region comprising an inverted staircase shaped STI structure. The step side wall spacers are removed from the X+2 step trenches. A planarized active area silicon structure is formed within the X+2 and final step trenches.
摘要翻译：一种形成倒置阶梯状STI结构的方法，包括以下步骤。提供具有上覆氧化物层的半导体衬底。衬底具有至少一对在其间限定STI区的有源区。首先在有源区内蚀刻氧化物层以形成第一级沟槽。第一级沟槽具有暴露的侧壁。连续的侧壁间隔件形成在所述暴露的第一阶梯沟槽侧壁上。使用先前形成的步骤侧壁间隔物作为掩模，将氧化物层连续蚀刻X + 1次，以在有效区域内形成连续的台阶沟槽。每个连续的台阶沟槽具有暴露的侧壁并且具有连续形成在连续的阶梯槽暴露侧壁上的侧壁间隔物。使用先前形成的步骤侧壁间隔物作为掩模来最后蚀刻氧化物层，以形成在活性区域内暴露衬底的最终步骤沟槽。 STI区域包括倒置的阶梯状STI结构。从X + 2台阶沟槽中移除台阶侧壁间隔物。平面化的有源区硅结构形成在X + 2和最后阶梯沟内。

128. 发明授权

US06436774B1 Method for forming variable-K gate dielectric 失效
公开(公告)号：US06436774B1
公开(公告)日：2002-08-20
申请号：US09769811
申请日：2001-01-26
申请人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L29/42376 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

129. 发明授权

US06403485B1 Method to form a low parasitic capacitance pseudo-SOI CMOS device 有权
标题翻译：形成低寄生电容伪SOI CMOS器件的方法
公开(公告)号：US06403485B1
公开(公告)日：2002-06-11
申请号：US09846177
申请日：2001-05-02
申请人： Elgin Quek , Ravi Sundaresan , Yang Pan , James Lee Yong Meng , Ying Keung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
发明人： Elgin Quek , Ravi Sundaresan , Yang Pan , James Lee Yong Meng , Ying Keung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
IPC分类号： H01L21302
CPC分类号： H01L21/76895
摘要： A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated SID extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the STI region separating those active areas. The hard mask layer is removed. Ions are implanted and driven in to form elevated S/D regions within the polysilicon layer adjacent to the gate electrodes to complete formation of transistors having elevated S/D regions.
摘要翻译：描述了一种形成具有可扩展的用于局部互连的源/漏（S / D）区域较高的伪SOI器件的方法。分离相邻有源区的浅沟槽隔离（STI）区域设置在半导体衬底内。多晶硅栅极电极和相关的SID延伸部分在其中硬掩模层覆盖每个栅极电极的有源区域内和衬底上制造。在每个栅电极的侧壁上形成电介质间隔物。沉积覆盖栅电极和衬底的多晶硅层。在硬掩模层上用抛光光阑抛光多晶硅层。多晶硅层被回蚀，由此多晶硅层相对于栅电极凹陷。此后，将多晶硅层蚀刻掉，覆盖STI区域，其中期望相邻的有源区域之间的间隔。如果在相邻的有源区域之间需要局部互连，则多晶硅层不会被覆盖在分离这些有源区域的STI区域之上。去除硬掩模层。离子被植入和驱动以在与栅电极相邻的多晶硅层内形成升高的S / D区，以完成具有升高的S / D区的晶体管的形成。

130. 发明授权

US06403484B1 Method to achieve STI planarization 失效
标题翻译：实现STI平坦化的方法
公开(公告)号：US06403484B1
公开(公告)日：2002-06-11
申请号：US09803187
申请日：2001-03-12
申请人： Victor Seng Keong Lim , Lap Chan , James Lee , Chen Feng , Wang Ling Goh
发明人： Victor Seng Keong Lim , Lap Chan , James Lee , Chen Feng , Wang Ling Goh
IPC分类号： H01L2100
CPC分类号： H01L21/31056 , H01L21/31053 , H01L21/76229
摘要： A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners. The second etch stop layer is polished away until the oxide layer overlying the first etch stop layer is exposed. The exposed oxide layer overlying the first etch stop layer is removed. The first and second etch stop layers are removed to complete the planarized shallow trench isolation regions in the manufacture of an integrated circuit device.
摘要翻译：描述了形成浅沟槽隔离的方法。通过第一蚀刻停止层将多个隔离沟槽蚀刻到下面的半导体衬底中。使用高密度等离子体化学气相沉积工艺（HDP-CVD）在第一蚀刻停止层和隔离沟槽内沉积氧化物层，其中在氧化物层填充隔离沟槽之后，沉积组分被中断，同时继续溅射组分直到第一蚀刻停止层的角部暴露在隔离沟槽的边缘处，由此隔离沟槽内的氧化物层与覆盖在第一蚀刻停止层上的氧化物层断开。此后，沉积在隔离沟槽内的氧化物层上的第二蚀刻停止层，覆盖在第一蚀刻停止层上的氧化物层和暴露的第一蚀刻停止层拐角。将第二蚀刻停止层抛光，直到暴露出覆盖在第一蚀刻停止层上的氧化物层。去除覆盖在第一蚀刻停止层上的暴露的氧化物层。去除第一和第二蚀刻停止层以在集成电路器件的制造中完成平坦化的浅沟槽隔离区。

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