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111. 发明授权

US06292402B1 Prefetch write driver for a random access memory 失效
标题翻译：为随机存取存储器预取写入驱动程序
公开(公告)号：US06292402B1
公开(公告)日：2001-09-18
申请号：US09456589
申请日：1999-12-08
申请人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
发明人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
IPC分类号： G11C1604
CPC分类号： G11C7/1072 , G11C7/1078
摘要： A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.
摘要翻译：用于随机存取存储器（RAM）的预取输入写入驱动器和包括预取输入写入驱动器的RAM。预取输入写入驱动器特别适用于同步动态RAM（SDRAM）。预取输入写入驱动器包括数据输入级接收数据，使能级接收对应的数据使能，以及写入驱动器，响应于写入信号和相应的使能级状态向存储器阵列提供接收到的数据。数据级和使能级可以各自包括两个或多个串联连接的三状态驱动器和每个三状态驱动器的输出端的锁存器。当数据通过数据阶段时，相应的使能状态通过使能阶段。如果使能状态指示要将数据级中的数据写入阵列，则将数据传送到RAM阵列。

112. 发明授权

US06272062B1 Semiconductor memory with programmable bitline multiplexers 有权
标题翻译：具有可编程位线多路复用器的半导体存储器
公开(公告)号：US06272062B1
公开(公告)日：2001-08-07
申请号：US09583596
申请日：2000-05-31
申请人： Gerhard Mueller , Toshiaki Kirihata , Dmitry Netis
发明人： Gerhard Mueller , Toshiaki Kirihata , Dmitry Netis
IPC分类号： G11C800
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C8/12 , G11C11/4097
摘要： There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups; at least one sense amplifier; a first and a second multiplexer; and at least one programmable control device. Each multiplexer is adapted to couple at least one of the groups to the amplifier. The programmable control device is adapted to control the first and said second multiplexers. In one embodiment, the programmable control device is adapted to control the multiplexers independently.
摘要翻译：提供一种半导体存储器件，其包括：以至少两组布置的多个存储单元; 至少一个读出放大器; 第一和第二多路复用器; 和至少一个可编程控制装置。每个多路复用器适于将至少一个组耦合到放大器。可编程控制装置适于控制第一和第二多路复用器。在一个实施例中，可编程控制装置适于独立地控制多路复用器。

113. 发明授权

US06259309B1 Method and apparatus for the replacement of non-operational metal lines in DRAMS 失效
标题翻译：用于替代DRAMS中的非操作金属线的方法和装置
公开(公告)号：US06259309B1
公开(公告)日：2001-07-10
申请号：US09305434
申请日：1999-05-05
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： G05F1116
CPC分类号： G11C29/80 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.
摘要翻译：一种半导体集成电路器件，包括用于替换用于连接到电路块的非操作金属线的冗余金属线。本发明还包括一种用于将有缺陷或其它不可操作的导电数据线与其所连接的电路块分离的方法，以及通过将其连接到相同的电路块来用冗余线代替有缺陷的导电数据线。不需要备用导电块。冗余金属线可以在集成电路器件内的多个层级中使用。

114. 发明授权

US06246630B1 Intra-unit column address increment system for memory 失效
标题翻译：内存单位列地址增量系统
公开(公告)号：US06246630B1
公开(公告)日：2001-06-12
申请号：US09017011
申请日：1998-02-02
申请人： Kohji Hosokawa , Toshiaki Kirihata
发明人： Kohji Hosokawa , Toshiaki Kirihata
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： A system and method is disclosed herein for providing column address increment pipelining within a single physically contiguous storage array, such as a left or a right unit of a double unit. Thereby, a multiple bank arrangement is provided within a double unit which permits column address increment pipelining to be performed within each bank thereof.
摘要翻译：本文公开的系统和方法用于在单个物理上连续的存储阵列（诸如双单元的左单位或右单元）内提供列地址增量流水线。因此，在双单元内提供多列布置，其允许在其每个库内执行列地址增量流水线化。

115. 发明授权

US06195300B1 CBR refresh control for the redundancy array 有权
标题翻译：冗余阵列的CBR刷新控制
公开(公告)号：US06195300B1
公开(公告)日：2001-02-27
申请号：US09536185
申请日：2000-03-24
申请人： Toshiaki Kirihata , Alexander Mitwalsky
发明人： Toshiaki Kirihata , Alexander Mitwalsky
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： According to one aspect of the invention, there is provided a method for refreshing memory cells in semiconductor memories. The method includes the steps of providing a semiconductor memory having memory cells and redundancy memory cells in at least one memory array and an associated redundancy memory array, respectively. The memory cells and the redundancy memory cells are independently refreshed, using addresses generated by a row address counter and a redundancy address counter, respectively. The method optionally includes the step of disabling redundancy wordlines coupled to unused redundancy memory cells, using a master fuse signal corresponding to a master fuse of the semiconductor memory.
摘要翻译：根据本发明的一个方面，提供一种刷新半导体存储器中的存储单元的方法。该方法包括以下步骤：分别在至少一个存储器阵列和相关联的冗余存储器阵列中提供具有存储器单元和冗余存储单元的半导体存储器。使用地址计数器和冗余地址计数器分别产生的地址，独立刷新存储单元和冗余存储单元。该方法可选地包括使用与半导体存储器的主熔丝相对应的主熔丝信号来禁用耦合到未使用的冗余存储器单元的冗余字线的步骤。

116. 发明授权

US06185135B2 Robust wordline activation delay monitor using a plurality of sample wordlines 有权
标题翻译：使用多个样本字线的稳健的字线激活延迟监视器
公开(公告)号：US06185135B2
公开(公告)日：2001-02-06
申请号：US09225340
申请日：1999-01-05
申请人： Dmitry G. Netis , L. Brian Ji , Toshiaki Kirihata
发明人： Dmitry G. Netis , L. Brian Ji , Toshiaki Kirihata
IPC分类号： G11C700
CPC分类号： G11C5/063
摘要： A wordline activation delay monitor circuit is disclosed wherein at least one sample wordline and a sample wordline redundancy are located within the same data-storing array region of a memory, and a sample wordline selector is coupled to activate the sample wordline or sample wordline redundancy based on the state of a nonvolatile input. The wordline selector circuit may include one or both of a row decoder circuit or a wordline driver circuit which have substantially the same structure and location as row decoder circuits and wordline driver circuits used to activate wordlines within the data-storing array region.
摘要翻译：公开了一种字线激活延迟监视电路，其中至少一个采样字线和采样字线冗余位于存储器的相同数据存储阵列区域内，并且采样字线选择器被耦合以激活采样字线或采样字线冗余处于非易失性输入状态。字线选择器电路可以包括行解码器电路或字线驱动器电路中的一个或两个，其具有与用于激活数据存储阵列区域内的字线的行解码器电路和字线驱动器电路基本相同的结构和位置。

117. 发明授权

US06178126B1 Memory and system configuration for programming a redundancy address in an electric system 有权
标题翻译：用于编程电气系统中冗余地址的存储器和系统配置
公开(公告)号：US06178126B1
公开(公告)日：2001-01-23
申请号：US09534423
申请日：2000-03-23
申请人： Toshiaki Kirihata , Paul W. Coteus , Warren E. Maule , Steven Tomashot
发明人： Toshiaki Kirihata , Paul W. Coteus , Warren E. Maule , Steven Tomashot
IPC分类号： G11C1300
CPC分类号： G11C29/72 , G11C29/785
摘要： A redundancy address in a plurality of memory devices is identified by at least two protocols available in an electric system. The first protocol is a mode register set command (or extended mode register set command). A chip select signal determines one of a plurality of memory modules, where a memory device is identified with at least one data port. Alternatively, a data strobe port or a data mask port may be preferably used for the selection of the memory devices instead of using the data port. The second protocol is a RAM access command which identifies a defective memory cell address (redundancy address) within the selected RAM by way of a plurality of address ports (ADRs). A redundancy address programming method is realized by way of electrically programmable fuses or by dynamically programmable redundancy latches integrated in each memory. The electric system configuration preferably includes a non-volatile storage device for storing a data port organization for the memory devices. Therein, the relation between the system memory data bus and the memory data ports for the memory devices are recognized by a memory controller. A microprocessor in the electric system is used for testing the memories and for analyzing the redundancy address. The present invention further includes a post device identification protocol to effectively debug field problems.
摘要翻译：多个存储设备中的冗余地址由电气系统中可用的至少两种协议来识别。第一个协议是模式寄存器设置命令（或扩展模式寄存器设置命令）。芯片选择信号确定多个存储器模块中的一个，其中存储器件被识别为具有至少一个数据端口。或者，可以优选地使用数据选通端口或数据掩码端口来选择存储设备，而不是使用数据端口。第二协议是RAM访问命令，其通过多个地址端口（ADR）识别所选择的RAM内的有缺陷的存储器单元地址（冗余地址）。通过电可编程熔丝或集成在每个存储器中的动态可编程冗余锁存器实现冗余地址编程方法。电气系统配置优选地包括用于存储用于存储器件的数据端口组织的非易失性存储设备。其中，存储器控制器识别系统存储器数据总线与存储器件的存储器数据端口之间的关系。电气系统中的微处理器用于测试存储器和分析冗余地址。本发明还包括有效调试现场问题的后期设备识别协议。

118. 发明授权

US6166981A Method for addressing electrical fuses 有权
标题翻译：电气保险丝寻址方法
公开(公告)号：US6166981A
公开(公告)日：2000-12-26
申请号：US512922
申请日：2000-02-25
申请人： Toshiaki Kirihata , Gabriel Daniel
发明人： Toshiaki Kirihata , Gabriel Daniel
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/802
摘要： A memory device that includes a plurality of data storage cells; at least one redundancy data storage cell; a redundancy match detection circuit; and a means for coupling programmable fuses to the redundancy match detection circuit, wherein a defective data storage is replaced by one redundancy data storage when the redundancy match detection detects a pre-determined condition set by said programmable fuse is described. Decoding is accomplished by a data bus selecting the e-fuse to be blown. The data bus is also used for reading the state of the e-fuses to ensure that the e-fuses are correctly blown. Power is effectively applied to the selected e-fuses while sharing the data bus for e-fuse decoding and verification. In order to reduce the number of communication channels between e-fuses and the redundancy match detection circuitry, the transfer operation uses time multiplexing, allowing e-fuse information to be transferred to the redundancy match detection circuitry sequentially. The actual time multiplexing operation for performing the transfer is preferably enabled only after the chip power-up state.
摘要翻译：一种包括多个数据存储单元的存储器件; 至少一个冗余数据存储单元; 冗余匹配检测电路; 以及用于将可编程保险丝耦合到冗余匹配检测电路的装置，其中描述了当冗余匹配检测检测到由所述可编程熔丝设置的预定条件时，由一个冗余数据存储器替换有缺陷的数据存储器。通过选择要熔断的电熔丝的数据总线实现解码。数据总线还用于读取电子保险丝的状态，以确保电子保险丝正确吹扫。电源有效地应用于选定的电子保险丝，同时共享用于电子熔丝解码和验证的数据总线。为了减少电子熔断器与冗余匹配检测电路之间的通信信道的数量，传输操作使用时间复用，允许电子熔丝信息被顺序传送到冗余匹配检测电路。用于执行传送的实际时间多路复用操作优选仅在芯片上电状态之后才能使能。

119. 发明授权

US6115308A Sense amplifier and method of using the same with pipelined read, restore and write operations 有权
标题翻译：感应放大器和使用流水线读取，恢复和写入操作的方法
公开(公告)号：US6115308A
公开(公告)日：2000-09-05
申请号：US335092
申请日：1999-06-17
申请人： David R. Hanson , Toshiaki Kirihata
发明人： David R. Hanson , Toshiaki Kirihata
IPC分类号： G11C11/413 , G11C7/06 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/419 , G11C7/00 , G11C7/02
CPC分类号： G11C7/1039 , G11C7/06
摘要： A method of performing overlapping operations with a memory device may have a sense amplifier circuit and two drivers connected to the sense amplifier circuit. Two data bus lines may be connected to the sense amplifier circuit to receive data signals. The method may include applying a first equalize signal and second equalize signal to the sense amplifier circuit to allow the sense amplifier circuit to receive the data signals across the data bus lines, applying a switch signal to the sense amplifier circuit to connect the data bus lines to a read data bus, and changing a state of the first equalize signal such that the data bus lines either receive new data or the data bus lines are equalized to a predetermined voltage while the data is on the read data bus and is capable of being read.
摘要翻译：与存储器件执行重叠操作的方法可以具有读出放大器电路和连接到读出放大器电路的两个驱动器。两条数据总线可以连接到读出放大器电路以接收数据信号。该方法可以包括将第一均衡信号和第二均衡信号施加到读出放大器电路，以允许读出放大器电路跨数据总线接收数据信号，将开关信号施加到读出放大器电路以连接数据总线读取数据总线，并且改变第一均衡信号的状态，使得数据总线线路接收新数据或数据总线线路均等于预定电压，同时数据位于读数据总线上并且能够被读。

120. 发明授权

US6069815A Semiconductor memory having hierarchical bit line and/or word line architecture 失效
标题翻译：具有分层位线和/或字线架构的半导体存储器
公开(公告)号：US6069815A
公开(公告)日：2000-05-30
申请号：US993538
申请日：1997-12-18
申请人： Gerhard Mueller , Toshiaki Kirihata , Hing Wong
发明人： Gerhard Mueller , Toshiaki Kirihata , Hing Wong
IPC分类号： G11C11/401 , G11C7/18 , G11C8/14 , G11C16/06 , G11C5/06
CPC分类号： G11C7/18 , G11C8/14
摘要： Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F.sup.2, includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.
摘要翻译：公开了具有分级位线和/或字线架构的半导体存储器。在一个实施例中，具有特别适合于小于8F2的小区的分层位线架构的存储器包括每列中的主位线对，包括彼此垂直间隔开的部分的第一和第二主位线。第一和第二主位线在垂直方向上相对于彼此扭曲，使得第一主位线交替地覆盖并位于第二主位线下方。每列中的多个局部位线对耦合到存储器单元，其中至少一个局部位线耦合到主位线。在其他实施例中，公开了分层字线配置，包括主字线，子主字线和本地字线，经由开关，电触点或电路彼此电互连。

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