会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Flexible row redundancy system
    • 灵活的行冗余系统
    • US07404113B2
    • 2008-07-22
    • US11031138
    • 2005-01-07
    • Louis L. HsuGregory J. FredemanRajiv V. JoshiToshiaki Kirihata
    • Louis L. HsuGregory J. FredemanRajiv V. JoshiToshiaki Kirihata
    • G11C29/00
    • G11C29/808
    • A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
    • 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块,用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 复制逻辑模块被编程为根据可选择的修复字段大小将至少一个故障地址复制到存储在对应于预定数量的存储体的行熔丝阵列中的行熔丝信息中。
    • 7. 发明授权
    • High performance gain cell architecture
    • 高性能增益单元架构
    • US06845059B1
    • 2005-01-18
    • US10604109
    • 2003-06-26
    • Matthew R. WordemanJohn E. BarthToshiaki Kirihata
    • Matthew R. WordemanJohn E. BarthToshiaki Kirihata
    • G11C7/10G11C8/16G11C11/406G11C11/4096G11C8/00
    • G11C8/16G11C7/106G11C7/1087G11C11/40603G11C11/40615
    • A memory architecture that utilizes single-ended dual-port destructive write memory cells and a local write-back buffer is described. Each cell has separate read and write ports that make it possible to read-out data from cells on one wordline in the array, and subsequently write-back to those cells while simultaneously reading-out the cell on another wordline in the array. By implementing an array of sense amplifiers such that one amplifier is coupled to each read bitline, and a latch receiving the result of the sensed data and delivering this data to the write data lines, it is possible to ‘pipeline’ the read-out and write-back phases of the read cycle. This allows for a write-back phase from one cycle to occur simultaneously with the read-out phase of another cycle. By extending the operation of the latch to accept data either from the sense amplifier, or from the memory data inputs, modified by the column address and masking bits, it is also possible to pipeline the read-out and the modify-write-back phases of a write cycle, allowing them to occur simultaneously. The architecture preferably employs a nondestructive read memory cell such as 2T or 3T gain cells, achieving an SRAM-like cycle and access times with a smaller and more SER immune memory cell.
    • 描述了利用单端双端口破坏性写存储器单元和本地回写缓冲器的存储架构。 每个单元都具有单独的读取和写入端口,可以从阵列中的一个字线上的单元读出数据,随后将其写回到这些单元格,同时读出数组中另一个字线上的单元格。 通过实现读出放大器的阵列,使得一个放大器耦合到每个读取位线,以及一个接收感测数据的结果并将该数据传送到写入数据线的锁存器,可以“管理”读出和 读周期的回写阶段。 这允许来自一个周期的回写阶段与另一个周期的读出阶段同时发生。 通过扩展锁存器的操作以接受来自读出放大器或由存储器数据输入的数据,由列地址和掩码位修改,还可以管理读出和修改回写阶段 的写周期,允许它们同时发生。 该架构优选采用非破坏性读取存储器单元,例如2T或3T增益单元,通过较小和更多的SER免疫存储单元实现SRAM类周期和访问时间。
    • 9. 发明授权
    • Wordline decoder system and method
    • 字线解码器系统和方法
    • US06400639B1
    • 2002-06-04
    • US09712628
    • 2000-11-14
    • Brian L. JiToshiaki KirihataDmitry G. Netis
    • Brian L. JiToshiaki KirihataDmitry G. Netis
    • G11C800
    • G11C8/12G11C8/08
    • A memory decoder system is disclosed. In an exemplary embodiment of the invention, the system includes a matrix of memory cells, arranged into rows and columns, with a plurality of wordline drivers corresponding to each row in the matrix. A group of wordline driver-decoder blocks each contains a subset of the plurality of wordline drivers therein, with each of the wordline driver-decoder blocks being separated by a row control block. The row control block includes control circuitry for the wordline drivers. For any given wordline driver-decoder block, a first group of wordline drivers contained therein is controlled by a row control block located on one side of the given wordline driver-decoder block, while a second group of wordline drivers contained therein is controlled by a row control block located on an opposite side of the given wordline driver-decoder block.
    • 公开了一种存储器解码器系统。 在本发明的示例性实施例中,系统包括排列成行和列的存储器单元阵列,其中多个字线驱动器对应于矩阵中的每一行。 一组字线驱动器 - 解码器块每个包含多个字线驱动器的子集,其中每个字线驱动器 - 解码器块由行控制块分隔。 行控制块包括用于字线驱动器的控制电路。 对于任何给定的字线驱动器 - 解码器块,其中包含的第一组字线驱动器由位于给定字线驱动器 - 解码器块的一侧上的行控制块控制,而其中包含的第二组字线驱动器由 行控制块位于给定字线驱动器 - 解码器块的相对侧。
    • 10. 发明授权
    • Defect management engine for generating a unified address to access memory cells in a primary and a redundancy memory array
    • 缺陷管理引擎,用于生成统一的地址,以访问主和冗余存储器阵列中的存储单元
    • US06243306B1
    • 2001-06-05
    • US09619257
    • 2000-07-19
    • Toshiaki Kirihata
    • Toshiaki Kirihata
    • G11C700
    • G11C29/76G11C29/808
    • A method and apparatus for eliminating defects present in memory devices by way of a defect management engine (DME) is described. The DME integrates a plurality of defective address cells and redundancy address cells within an array. The defective address cells store addresses for accessing defective cells in a main memory. The redundancy address cells store addresses for accessing redundancy cells within a redundancy memory. The address data in the defective address cells is compared to the address input of the DME, thereby providing a redundancy match detection scheme. When no match occurs, the DME outputs the address input of the DME, which allows the main memory to be accessed when operating in a normal mode. When a match occurs, the DME outputs the address read from the redundancy address cells, which allows the redundancy memory to be accessed when operating in a redundancy mode.
    • 描述了通过缺陷管理引擎(DME)消除存储在设备中的缺陷的方法和装置。 DME在阵列内集成了多个缺陷地址单元和冗余地址单元。 缺陷地址单元存储用于访问主存储器中的有缺陷单元的地址。 冗余地址单元存储用于访问冗余存储器内的冗余单元的地址。 将缺陷地址单元中的地址数据与DME的地址输入进行比较,从而提供冗余匹配检测方案。 当不匹配时,DME输出DME的地址输入,允许在正常模式下工作时访问主存储器。 当匹配发生时,DME输出从冗余地址单元读取的地址,这允许在冗余模式下操作时访问冗余存储器。