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1. 发明授权

US6069815A Semiconductor memory having hierarchical bit line and/or word line architecture 失效
标题翻译：具有分层位线和/或字线架构的半导体存储器
公开(公告)号：US6069815A
公开(公告)日：2000-05-30
申请号：US993538
申请日：1997-12-18
申请人： Gerhard Mueller , Toshiaki Kirihata , Hing Wong
发明人： Gerhard Mueller , Toshiaki Kirihata , Hing Wong
IPC分类号： G11C11/401 , G11C7/18 , G11C8/14 , G11C16/06 , G11C5/06
CPC分类号： G11C7/18 , G11C8/14
摘要： Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F.sup.2, includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.
摘要翻译：公开了具有分级位线和/或字线架构的半导体存储器。在一个实施例中，具有特别适合于小于8F2的小区的分层位线架构的存储器包括每列中的主位线对，包括彼此垂直间隔开的部分的第一和第二主位线。第一和第二主位线在垂直方向上相对于彼此扭曲，使得第一主位线交替地覆盖并位于第二主位线下方。每列中的多个局部位线对耦合到存储器单元，其中至少一个局部位线耦合到主位线。在其他实施例中，公开了分层字线配置，包括主字线，子主字线和本地字线，经由开关，电触点或电路彼此电互连。

2. 发明授权

US5691946A Row redundancy block architecture 失效
标题翻译：行冗余块架构
公开(公告)号：US5691946A
公开(公告)日：1997-11-25
申请号：US758783
申请日：1996-12-03
申请人： John DeBrosse , Toshiaki Kirihata , Hing Wong
发明人： John DeBrosse , Toshiaki Kirihata , Hing Wong
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C29/80 , G11C29/808 , G11C29/84
摘要： Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator.
摘要翻译：有效减少设计空间的行冗余控制电路与字方向平行排列，并配置在冗余块的底部。通过引入（1）与本地行冗余线共享的分裂全局总线，（2）半长度单向行冗余字线使能信号线，可以有效地布置冗余控制块这允许节省空间，以及（3）分布式字线使能解码器被设计为利用节省的空间。由地址与时序偏差引起的非法正常/冗余访问问题也已解决。通过使用其相邻的冗余匹配检测在本地给出该检测所需的定时。这允许电路作为地址驱动电路完全操作，导致快速可靠的冗余匹配检测。此外，通过使用行冗余匹配检测来生成采样字线使能信号（SWLE）。一个双输入或门允许SWLE设置采样字线（SWL）的时间与字线使能（WLE）信号设置字线（WL）的时间相同。无论模式如何，SWLE设置SWL的时间保持一致，从而消除了现有的可靠性问题。该双输入OR门与行冗余匹配检测相结合，可作为理想的采样字线使能发生器。

3. 发明授权

US5610867A DRAM signal margin test method 失效
标题翻译： DRAM信号余量测试方法
公开(公告)号：US5610867A
公开(公告)日：1997-03-11
申请号：US535446
申请日：1995-09-28
申请人： John K. DeBrosse , Toshiaki Kirihata , Hing Wong
发明人： John K. DeBrosse , Toshiaki Kirihata , Hing Wong
IPC分类号： G11C11/401 , G11C11/409 , G11C11/4091 , G11C29/50 , G11C7/00 , G11C29/00
CPC分类号： G11C11/4091 , G11C29/50 , G06F2201/81 , G11C11/401
摘要： In the Preferred embodiment of the present invention, a bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level. Additionally, because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, as in prior art signal margin tests, cell signal margin is tested by varying cell signal. V.sub.S may be selected to determine both a high and a low signal margin.
摘要翻译：在本发明的优选实施例中，位线对通过一对高电阻通过门耦合到感测放大器。在感测期间，高电阻通过门与存储在位线对上的电荷一起作为有效地用于感测放大器的高电阻无源负载。控制电路选择性地接通和断开位线均衡，与选择性地将均衡电压或设定电压通过感测放大器和主动感测放大器负载相一致。此外，在设置之后，感测放大器通过低电阻列选择通孔选择性地连接到LDL。因此，当位线电压基本保持不变时，感测放大器会快速放电连接的LDL对之一。因此，数据从感测放大器传递到第二读出放大器和芯片外。数据传送到LDL后，控制电路使主动感测放大器负载将感测放大器的高端拉到一个完整的电平。此外，由于控制电路使用均衡电压来禁用读出放大器，所以可以以新的方式测试单元信号余量。代替检测放大器参考电压，如现有技术的信号余量测试，通过改变单元信号来测试单元信号余量。可以选择VS来确定高和低信号余量。

4. 发明授权

US5963489A Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device 失效
标题翻译：用于可修复半导体存储器件中冗余字线替换的方法和装置
公开(公告)号：US5963489A
公开(公告)日：1999-10-05
申请号：US47086
申请日：1998-03-24
申请人： Toshiaki Kirihata , John K. DeBrosse , Yohji Watanabe , Hing Wong
发明人： Toshiaki Kirihata , John K. DeBrosse , Yohji Watanabe , Hing Wong
IPC分类号： G11C29/04 , G11C29/00 , G11C7/00
CPC分类号： G11C29/806 , G11C29/848
摘要： A method and apparatus for repairing a semiconductor memory device. A row redundancy replacement arrangement is provided to repair the memory device consisting of a first plurality of redundant true word lines and a second plurality of redundant complement word lines to simultaneously replace the same first number of first normal word lines and the same second number of the normal complement word lines. An address reordering scheme, preferably implemented as a word line selector circuit and controlled by redundancy control logic and address inputs, allows the redundant true (complement) word lines to replace the normal true (complement) word lines when making the repair. The redundancy replacement arrangement ensures that consistency of the bit map is maintained at all times, irrespective whether the memory device operates in a normal or in a redundancy mode. This approach introduces an added flexibility of incorporating the redundancy replacement without affecting the column access speed.
摘要翻译：一种用于修复半导体存储器件的方法和装置。提供行冗余替换布置以修复由第一多个冗余真字字线和第二多个冗余补码字线组成的存储器件，以同时替换相同的第一数量的第一正常字线和相同的第二数目的第正常补码字线。地址重排序方案优选地实现为字线选择器电路并由冗余控制逻辑和地址输入控制，允许冗余的真（补）字线在进行修复时替换正常的真（补）字线。冗余替换布置确保始终保持位图的一致性，而不管存储器件是以正常操作还是以冗余模式操作。这种方法引入了增加冗余替换的灵活性，而不影响列访问速度。

5. 发明授权

US5745430A Circuit and method to externally adjust internal circuit timing 失效
公开(公告)号：US5745430A
公开(公告)日：1998-04-28
申请号：US777559
申请日：1996-12-30
申请人： Hing Wong , Toshiaki Kirihata , Bozidar Krsnik
发明人： Hing Wong , Toshiaki Kirihata , Bozidar Krsnik
IPC分类号： G06F1/06 , G01R31/30 , G06F1/08 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G01R31/3016
摘要： A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.

6. 发明授权

US5619460A Method of testing a random access memory 失效
标题翻译：测试随机存取存储器的方法
公开(公告)号：US5619460A
公开(公告)日：1997-04-08
申请号：US477061
申请日：1995-06-07
申请人： Toshiaki Kirihata , Hing Wong
发明人： Toshiaki Kirihata , Hing Wong
IPC分类号： G11C29/12 , G11C29/06 , G11C29/10 , G11C29/00
CPC分类号： G11C29/10
摘要： A method of testing a RAM. The RAM array is arranged in rows and columns. The rows are grouped into word line groups. The method includes the steps of: a) asserting an array select signal; b) selecting a group of rows in the array; c) selecting at least one row of the selected group of rows; and, d) repeating steps b and c until all of the groups are selected. Array Sense Amps may be set when the first group is selected and remain set until the last group is selected. In one test, word lines in all of the selected rows are activated and remain activated until the final selected row is selected. In a second test, word lines in selected groups are toggled with RAS. If a group contains a known defective word line, that group is either not addressed or its selection is disabled. In each selected group, one row, alternating rows or, all of the rows may be selected.
摘要翻译：一种测试RAM的方法。 RAM阵列以行和列排列。行被分组成字线组。该方法包括以下步骤：a）断言阵列选择信号; b）在数组中选择一组行; c）选择所选择的一组行中的至少一行; 和d）重复步骤b和c，直到选择所有组。当选择第一组时，可以设置阵列传感放大器，并保持设置，直到选择最后一个组。在一个测试中，所有选定行中的字线都被激活，并保持激活状态，直到选中最后一行。在第二个测试中，所选组中的字线与RAS切换。如果组中包含已知的有缺陷的字线，则该组不被寻址或其选择被禁用。在每个选定的组中，可以选择一行，交替行或全部行。

7. 发明授权

US5559739A Dynamic random access memory with a simple test arrangement 失效
标题翻译：动态随机存取存储器，具有简单的测试方案
公开(公告)号：US5559739A
公开(公告)日：1996-09-24
申请号：US535702
申请日：1995-09-28
申请人： John K. DeBrosse , Toshiaki Kirihata , Hing Wong
发明人： John K. DeBrosse , Toshiaki Kirihata , Hing Wong
IPC分类号： G01R31/28 , G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/4094 , G11C29/50 , G11C7/00 , G11C29/00
CPC分类号： G11C11/4091 , G11C11/4094 , G11C29/50 , G11C11/401
摘要： A Dynamic Random Access Memory (DRAM) including an array of memory cells arranged in rows and columns, a word line in each row responsive to a row address and, a pair of complementary bit lines in each column. The DRAM also includes a sense amp in each column connected between a sense enable and the pair of complementary bit lines. The sense amp is a pair of cross coupled NFETs, with the sources of the NFETs connected to the sense amp enable. A bit line pre-charge is connected to each pair of complementary bit lines. The bit line pre-charge is connected between the complementary bit line pair and a reference voltage. A test control circuit selectively holds the sense amp disabled and the bit line pairs in a pre-charge state in response to a test control signal. An active sense amp load connected between the sense amp and a load enable latches data in the sense amp. The active sense amp load is a pair of cross coupled PFETs connected to the sense amp with the sources of the PFETs connected to the load enable. Optionally, each column may include a plurality of bit line pairs, each pair connected to a mux input. In this embodiment, the sense amp is connected between the mux's output and the sense amp enable. Because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, the voltage stored in the cells is varied. So, cell signal margin is tested by varying cell signal V.sub.S. V.sub.S may be selected to determine both a high and a low signal margin.
摘要翻译：一种动态随机存取存储器（DRAM），包括排列成行和列的存储器单元的阵列，每行中的字线响应于行地址，以及每列中的一对互补位线。 DRAM还包括连接在感测使能和该对互补位线之间的每列中的感测放大器。感测放大器是一对交叉耦合的NFET，其中NFET的源极连接到感测放大器使能。位线预充电连接到每对互补位线。位线预充电连接在互补位线对和参考电压之间。测试控制电路响应于测试控制信号选择性地将感测放大器禁用和位线对保持在预充电状态。连接在感测放大器和负载使能之间的主动感测放大器负载锁定读出放大器中的数据。主动感测放大器负载是连接到感测放大器的一对交叉耦合PFET，PFET的源极连接到负载使能。可选地，每列可以包括多个位线对，每对连接到多路复用器输入。在本实施例中，感测放大器连接在多路复用器的输出和读出放大器使能之间。由于控制电路使用均衡电压来禁用读出放大器，所以可以以新的方式测试单元信号余量。代替改变感测放大器参考电压，存储在单元中的电压是变化的。因此，通过改变单元信号VS来测试单元信号余量。可以选择VS来确定高和低信号余量。

8. 发明授权

US5848008A Floating bitline test mode with digitally controllable bitline equalizers 失效
标题翻译：具有数字可控位线均衡器的浮动位线测试模式
公开(公告)号：US5848008A
公开(公告)日：1998-12-08
申请号：US937528
申请日：1997-09-25
申请人： Toshiaki Kirihata , Hing Wong , Bozidar Krsnik
发明人： Toshiaki Kirihata , Hing Wong , Bozidar Krsnik
IPC分类号： G01R31/28 , G11C11/401 , G11C29/04 , G11C29/50 , G11C29/56 , G11C7/00
CPC分类号： G11C29/50
摘要： A method for generating a floating bitline test mode using digitally controllable bitline equalizers is provided. The method utilizes digitally controlled dummy timing cycles to detect a leaky bitline during the floating bitline test mode. A negative pulsed TEST signal is generated to cause the bitline equalizers to go low and cause the floating bitline state. The implementation of dummy timing cycles eliminates the need for additional external control of internal timings during a bitline test mode. Upon the termination of the dummy timing cycle, the normal read operation continues without interruption.
摘要翻译：提供一种使用数字可控位线均衡器产生浮动位线测试模式的方法。该方法利用数字控制的虚拟定时周期来检测浮动位线测试模式期间的泄漏位线。产生负脉冲+ E，ovs TEST + EE信号，使位线均衡器变为低电平，并导致浮置位线状态。虚拟定时周期的实现消除了在位线测试模式期间对内部定时的额外外部控制的需要。在虚拟定时周期结束时，正常读取操作继续而不中断。

9. 发明授权

US5615164A Latched row decoder for a random access memory 失效
标题翻译：用于随机存取存储器的锁存行解码器
公开(公告)号：US5615164A
公开(公告)日：1997-03-25
申请号：US477063
申请日：1995-06-07
申请人： Toshiaki Kirihata , Hing Wong
发明人： Toshiaki Kirihata , Hing Wong
IPC分类号： G11C11/413 , G11C8/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/02 , G11C29/06 , G11C29/12 , G11C29/34 , G11C29/50 , G11C8/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/34 , G11C29/50 , G11C8/10 , G11C11/401
摘要： A latched row decoder for a Random Access Memory (RAM). The Decoder includes a set-reset latch that is set when addressed and remains set until reset by a PRE signal; address select logic; a reset device; and gated word line drives. The latch, when set, enables four word line drivers that are driven individually depending on two row address bits. During test, latched decoders may be selected sequentially and not reset, leaving drivers enabled until a test is complete. Thus some or all word lines may be driven simultaneously during test. A RAM including the latched decoder of the present invention has a normal random access mode and at least 4 test modes. The test modes are: Long t.sub.RAS word line disturb mode; toggled word line disturb mode; transfer gate stress mode; and a stress test mode.
摘要翻译：用于随机存取存储器（RAM）的锁存行解码器。解码器包括设置复位锁存器，其在寻址时被置位并保持置位，直到由PRE信号复位; 地址选择逻辑; 复位装置; 和门控驱动器。当锁存器置位时，可以根据两个行地址位单独驱动四个字线驱动器。在测试期间，锁存解码器可以顺序选择并且不复位，使驱动器启用，直到测试完成。因此，在测试期间可以同时驱动一些或所有字线。包括本发明的锁存解码器的RAM具有正常的随机存取模式和至少4个测试模式。测试模式为：长tRAS字线干扰模式; 切换字线干扰模式; 传输门应力模式; 和压力测试模式。

10. 发明授权

US5517442A Random access memory and an improved bus arrangement therefor 失效
标题翻译：随机存取存储器及其改进的总线布置
公开(公告)号：US5517442A
公开(公告)日：1996-05-14
申请号：US402790
申请日：1995-03-13
申请人： Toshiaki Kirihata , Yohji Watanabe , Hing Wong
发明人： Toshiaki Kirihata , Yohji Watanabe , Hing Wong
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C29/00 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/80 , G11C7/10
摘要： The present invention is a bus arrangement for a wide I/O Random Access Memory (RAM). The bus arrangement includes a global address bus which drives row/column predecoders and redundancy comparators placed at each edge of the memory array. Two banks of sixteen data I/O (DQs), one bank for each half chip, are placed at either end of the chip providing up to a .times.32 I/O organization. The main Read/Write Data lines (RWD) are more densely populated near the chip edge than the chip center to provide .times.4 and .times.8 options, as well. A local address bus is in the open space between the RWDs to redrive the global address lines at their quarter points.
摘要翻译：本发明是用于宽I / O随机存取存储器（RAM）的总线装置。总线布置包括全局地址总线，其驱动行/列预解码器和放置在存储器阵列的每个边缘处的冗余比较器。十六个数据I / O（DQ）的两组，每个半芯片的一个存储区，放置在芯片的任一端，提供一个x32 I / O组织。主芯片读/写数据线（RWD）在芯片边缘附近比芯片中心更密集，以提供x4和x8选项。本地地址总线位于RWD之间的开放空间，以便在其四分之一点重新启动全局地址线。

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